Copyright 2005 Cirrus Logic (All Rights Reserved)
MAR `05
DS638PP4
1
http://www.cirrus.com
Enhanced Universal Platform
System-on-Chip Processor
EP9315 Data Sheet
FEATURES
200-MHz ARM920T Processor
16-kbyte Instruction Cache
16-kbyte Data Cache
Linux
, Microsoft
Windows
CE-enabled MMU
100-MHz System Bus
MaverickCrunch
TM
Math Engine
Floating Point, Integer, and Signal Processing
Instructions
Optimized for digital music compression and
decompression algorithms.
Hardware interlocks allow in-line coding.
MaverickKey
TM
IDs
32-bit Unique ID can be used for DRM-compliant
128-bit random ID.
Integrated Peripheral Interfaces
32-bit SDRAM Interface (up to 4 Banks)
32-/16-bit SRAM / FLASH / ROM
Serial EEPROM Interface
EIDE (up to 2 devices)
1/10/100-Mbps Ethernet MAC
Three UARTs
Three-port USB 2.0 Full-speed Host (OHCI)
(12 Mbits per second)
LCD and Raster Interface with Graphics
Accelerator
IrDA Interface
PCMCIA Interface
Touchscreen Interface with ADC
8 x 8 Keypad Scanner
One Serial Peripheral Interface (SPI
TM
) Port
6-channel or 2-channel Serial Audio Interface (I
2
S)
2-channel, Low-cost Serial Audio Interface (AC'97)
2 High-resolution PWMs (16 bits each)
Internal Peripherals
12 Direct Memory Access (DMA) Channels
Real-time Clock with Software Trim
Dual PLL controls all clock domains.
Watchdog Timer
Two General-purpose 16-bit Timers
One General-purpose 32-bit Timer
One 40-bit Debug Timer
Interrupt Controller
Boot ROM
Package
352-pin PBGA
Unified
SDRAM I/F
Video/LCD
Controller
(3) USB
Hosts
EIDE
I/F
Ethernet
MAC
Bus
Bridge
Boot
ROM
MaverickKey
TM
12-channel DMA
SRAM & Flash I/F
PCMCIA
MaverickCrunch
TM
ARM920T
MMU
D-Cache
16KB
I-Cache
16KB
Processor Bus
Peripheral Bus
Serial
Audio
Interface
Interrupts
& GPIO
Clocks &
Timers
Keypad &
Touch
Screen I/F
(3) UARTs
w/
IrDA
Graphics
Accelerator
COMMUN
ICA
T
IONS
PORTS
US
ER INTERFACE
MEMORY AND STORAGE
2
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
EP9315
Enhanced Universal Platform SOC Processor
The EP9315 is an ARM920T-based system-on-a-chip
design with a large peripheral set targeted to a variety of
applications:
Thin Client Computers for Business and Home
Internet Radio
Internet Access Devices
Industrial Computers
Specialized Terminals
Point-of-sale Terminals
Test and Measurement Equipment
The ARM920T microprocessor core with separate
16-kbyte, 64-way set-associative instruction and data
caches is augmented by the MaverickCrunchTM co-
processor, enabling high-speed floating point
calculations.
MaverickKey
TM
unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
A high-performance 1/10/100-Mbps Ethernet media
access controller (EMAC) is included along with external
interfaces to SPI, I
2
S audio, Raster/LCD, IDE storage
peripherals, keypad, and touchscreen. A three-port USB
2.0 Full Speed Host (OHCI) (12 Mbits per second) and
three UARTs are included as well.
The EP9315 is a high-performance, low-power, RISC-
based, single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 200 MHz (184 MHz for industrial conditions). The
ARM core operates from a 1.8 V supply, while the I/O
operates at 3.3 V with power usage between 100 mW
and 750 mW (dependent on speed).
OVERVIEW
Table A. Change History
Revision
Date
Changes
PP1
January 2004
Initial Release.
PP2
July 2004
Update AC data.
Add ADC data.
PP3
Febuary 2005
Update electrical characteristics based upon more complete characterization data.
PP4
March 2005
Minor correction to block diagram on page 1. DD7 changed to pull down.
DS638PP4
Copyright 2005 Cirrus Logic (All Rights Reserved)
3
EP9315
Enhanced Universal Platform SOC Processor
Table of Contents
FEATURES .........................................................................................................1
OVERVIEW .........................................................................................................2
Processor Core - ARM920T ......................................................................................... 6
MaverickCrunchTM Math Engine .................................................................................. 6
MaverickKeyTM Unique ID ............................................................................................ 6
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6
IDE Interface ................................................................................................................ 7
Ethernet Media Access Controller (MAC) .................................................................... 7
Serial Interfaces (SPI, I2S and AC '97) ........................................................................ 7
Raster / LCD Interface ................................................................................................. 7
Graphics Accelerator ................................................................................................... 8
Touch Screen Interface with 12-bit Analog-to-digital Converter (ADC) ........................ 8
64-Key Keypad Interface ............................................................................................. 8
Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 9
Triple Port USB Host .................................................................................................... 9
Two-wire Interface ........................................................................................................ 9
Real-Time Clock with Software Trim .......................................................................... 10
PLL and Clocking ....................................................................................................... 10
Timers ........................................................................................................................ 10
Interrupt Controller ..................................................................................................... 10
Dual LED Drivers ....................................................................................................... 10
General Purpose Input/Output (GPIO) ....................................................................... 10
Reset and Power Management ..................................................................................11
Hardware Debug Interface ..........................................................................................11
Internal Boot ROM ......................................................................................................11
12-channel DMA Controller .........................................................................................11
PCMCIA Interface .......................................................................................................11
Electrical Specifications .................................................................................12
Absolute Maximum Ratings ....................................................................................... 12
Recommended Operating Conditions ........................................................................ 12
DC Characteristics ..................................................................................................... 13
Timings .............................................................................................................14
Memory Interface ....................................................................................................... 15
PCMCIA Interface ...................................................................................................... 30
IDE Interface .............................................................................................................. 32
Ethernet MAC Interface ............................................................................................ 45
Audio Interface ........................................................................................................... 47
AC'97 ........................................................................................................................ 51
LCD Interface ............................................................................................................ 52
ADC ........................................................................................................................... 53
JTAG .......................................................................................................................... 54
352 Pin BGA Package Outline .......................................................................55
352-Ball PBGA Diagram ........................................................................................... 55
352 Pin BGA Pinout (Bottom View) ........................................................................... 56
Acronyms and Abbreviations ........................................................................63
Units of Measurement .....................................................................................63
ORDERING INFORMATION ............................................................................64
4
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
EP9315
Enhanced Universal Platform SOC Processor
List of Figures
Figure 1. Timing Diagram Drawing Key .................................................................................14
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15
Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16
Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17
Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18
Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19
Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20
Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement .................... 21
Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement .................... 22
Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................ 23
Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................ 24
Figure 12. Static Memory Burst Read Cycle Timing Measurement .......................................25
Figure 13. Static Memory Burst Write Cycle Timing Measurement .......................................26
Figure 14. Static Memory Single Read Wait Cycle Timing Measurement ............................. 27
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement .............................. 28
Figure 16. Static Memory Turnaround Cycle Timing Measurement .......................................29
Figure 17. PCMCIA Read Cycle Timing Measurement .......................................................... 30
Figure 18. PCMCIA Write Cycle Timing Measurement .......................................................... 31
Figure 19. Register Transfer to/from Device .......................................................................... 33
Figure 20. PIO Data Transfer to/from Device ......................................................................... 35
Figure 21. Initiating an Ultra DMA data-in Burst ..................................................................... 37
Figure 22. Sustained Ultra DMA data-in Burst ....................................................................... 38
Figure 23. Host Pausing an Ultra DMA data-in Burst ............................................................. 38
Figure 24. Device Terminating an Ultra DMA data-in Burst ................................................... 39
Figure 25. Host Terminating an Ultra DMA data-in Burst ....................................................... 40
Figure 26. Initiating an Ultra DMA data-out Burst .................................................................. 41
Figure 27. Sustained Ultra DMA data-out Burst ..................................................................... 42
Figure 28. Device Pausing an Ultra DMA data-out Burst ....................................................... 42
Figure 29. Host Terminating an Ultra DMA data-out Burst ....................................................43
Figure 30. Device Terminating an Ultra DMA data-out Burst ................................................. 44
Figure 31. Ethernet MAC Timing Measurement ..................................................................... 46
Figure 32. TI Single Transfer Timing Measurement ............................................................... 48
Figure 33. Microwire Frame Format, Single Transfer ............................................................ 48
Figure 34. SPI Format with SPH=1 Timing Measurement ..................................................... 49
Figure 35. Inter-IC Sound (I2S) Timing Measurement ........................................................... 50
Figure 36. AC `97 Configuration Timing Measurement .......................................................... 51
Figure 37. LCD Timing Measurement .................................................................................... 52
Figure 38. ADC Transfer Function ......................................................................................... 53
Figure 39. JTAG Timing Measurement .................................................................................. 54
Figure 40. 352 Pin PBGA Pin Diagram .................................................................................. 55
Figure 40. 352 PIN BGA PINOUT ......................................................................................... 57
DS638PP4
Copyright 2005 Cirrus Logic (All Rights Reserved)
5
EP9315
Enhanced Universal Platform SOC Processor
List of Tables
Table A. Change History .......................................................................................................... 2
Table B. General Purpose Memory Interface Pin Assignments .............................................. 6
Table C. IDE Interface Pin Assignments .................................................................................. 7
Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7
Table E. Audio Interfaces Pin Assignment .............................................................................. 7
Table F. LCD Interface Pin Assignments ................................................................................ 8
Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8
Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8
Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9
Table J. Triple Port USB Host Pin Assignments ..................................................................... 9
Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9
Table L. Real-Time Clock with Pin Assignments ................................................................... 10
Table M.PLL and Clocking Pin Assignments ........................................................................ 10
Table N. External Interrupt Pin Assignment ........................................................................... 10
Table O. Dual LED Pin Assignments ..................................................................................... 10
Table P. General Purpose Input/Output Pin Assignment ...................................................... 11
Table Q. Reset and Power Management Pin Assignments ................................................... 11
Table R. Hardware Debug Interface ...................................................................................... 11
Table S. PCMCIA Interface ................................................................................................... 11
Table R. 352 Pin Diagram Dimensions .................................................................................. 56
Table S. Pin Descriptions ..................................................................................................... 60
Table T. Pin Multiplex Usage Information ............................................................................. 62
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