1
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Line Card Access Switch
Description
The CPC7583 is a monolithic solid state switch in a 28 pin
surface mount SOIC package. It provides the necessary
functions to replace three 2-Form-C electromechanical re-
lays on analog line cards found in Central Office, Access
and PBX equipment. The device contains solid state
switches for tip and ring line break, ring injection/ring re-
turn, line test access, test in access and ringing generator
testing. The CPC7583 requires only a +5V supply and of-
fers "break-before-make" or "make-before-break" switch
operation using simple logic level input control. The
CPC7583 has 4 versions. The CPC7583BA and the
CPC7583BC contain the integrated protection SCR while
the CPC7583BC and the CPC7583BD contain an extra
logic state which is detailed in later sections.
Features
Small 28 pin surface mount SOIC package
Monolithic IC reliability
Low matched RDS
ON
Eliminates the need for zero cross switching
Flexible switch timing to transition from ringing mode to
idle/talk mode
Clean, bounce free switching
Tertiary protection consisting of integrated current
limiting, thermal shutdown and SLIC protection
5V operation with power consumption <10mW
Intelligent battery monitor
Latched logic level inputs, no drive circuitry
Pin to pin compatible to the Lucent 7583 family
Block Diagram
Applications
Central office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
Fiber in the Loop (FITL)
Pair Gain System
Channel Banks
CPC7583
Ordering Information
Part #
Description
CPC7583BA
10 Pole with protection SCR
CPC7583BB
10 Pole without protection SCR
CPC7583BC
10 Pole extra logic state with
protection SCR
CPC7583BD
10 Pole extra logic state without
protection SCR
CPC7583BATR Tape and Reel Version
CPC7583BBTR Tape and Reel Version
CPC7583BCTR Tape and Reel Version
CPC7583BDTR Tape and Reel Version
DS-CPC7583-RE
R1
R2
Ring
TIP
Secondary
Protection
SW6
Test Out
SW1 Break
SW10
Test In
SW3
Ringing
Return
SW7
Ringing Test Return
SW8
Ringing Test
SW4
Ringing
Access
T
BAT (6)
R
BAT (23)
Ring Generator
V
BAT
Reference (28)
CPC7583BA
Battery
SLIC
SW9
Test In
SW5
Test Out
Break SW2
SCR and
TRIP Circuit
T
LINE (7)
R
LINE (22)
T
TESTout
(10)
T
RING
(8)
T
TESTin
(5)
R
TESTin (24)
R
RING
(20)
R
TESTout
(19)
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Rev. E
CPC7583
Absolute Maximum Ratings are stress ratings. Functional op-
eration of the device at these or any other conditions beyond
those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to the absolute maximum
ratings for extended period may degrade the device and effect
its reliability.
Electrical Characteristics
TA = -40
o
C to +85
o
C (unless otherwise specified)
Minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result
of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements.
1
V
BAT
is used only as a reference for internal protection circuitry.
If V
BAT
rises above -10V, the device will enter an all off state and will remain in the all off state until the battery voltage drops below -15V.
Power Supply Specifications
Supply
Min
Typ
Max
Unit
V
DD
+4.5
+5.0
+5.5
V
V
BAT
1
-19
-
-72
V
ESD Rating (HBM Model)
1000
Parameter
Min
Max
Units
Operating Temperature Range
-40
+110
C
Storage Temperature Range
-40
+150
C
Relative Humidity Range
5
95
%
Pin Soldering Temperature
-
+260
C
(t=10 s max)
+5V Power Supply
-
7
V
Battery Supply
-
-85
V
Logic Input Voltage
-
7
V
Logic Input to Switch Output Isolation
-
330
V
Switch Isolation
(SW1, SW2, SW3,
-
330
V
SW5, SW6, SW7, SW9,SW10)
Switch Isolation (SW4)
-
480
V
Switch Isolation (SW8)
-
235
V
Table 1. Break Switch, SW1 and SW2
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
+25oC
Vsw (differential)= -320V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +260V
+85oC
Vsw (differential)= -330V to Gnd
Isw
-
0.3
1
A
Vsw (differential)= -60V to +270V
-40oC
Vsw (differential)= -310V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +250V
RDSON (SW1,SW2):
+25oC
T
LINE
= +/-10 mA, +/-40mA, T
BAT
= -2V
V
-
14.5
-
+85oC
T
LINE
= +/-10 mA, +/-40mA, T
BAT
= -2V
V
-
20.5
28
-40oC
T
LINE
= +/-10 mA, +/-40mA, T
BAT
= -2V
V
-
10.5
-
RDSON Match
Per ON-resistance Test Condition of
Magnitude
-
0.15
0.8
SW1, SW2
R
ON
SW1-R
ON
SW2
DC Current Limit:
+25oC
Vsw (on) = +/- 10V
Isw
-
225
-
mA
+85oC
Vsw (on) = +/- 10V
Isw
80
150
-
mA
-40oC
Vsw (on) = +/- 10V
Isw
-
400
425
mA
Dynamic Current Limit:
Break switches in ON state, ringing
Isw
-
2.5
-
A
(t=<0.5
s)
access switches OFF, apply +/- 1000V
at 10/1000
s pulse, appropriate
secondary protection in place.
Logic Input to Switch Output Isolation:
+25oC
Vsw (T
LINE
, R
LINE
) = +/-320V
Isw
-
0.1
1
A
Logic Inputs = Gnd
+85oC
Vsw (T
LINE
, R
LINE
) = +/-330V
Isw
-
0.3
1
A
Logic Inputs = Gnd
-40oC
Vsw (T
LINE
, R
LINE
) = +/-310V
Isw
-
0.1
1
A
Logic Inputs = Gnd
dv/dt Sensitivity
1
-
-
-
200
-
V/
s
1
Applied voltage is 100 Vp-p square wave at 100Hz.
CPC7583
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3
Rev. E
Table 2. Ring Return Switch, SW3
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current
+25oC
Vsw (differential)= -320V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +260V
+85oC
Vsw (differential)= -330V to Gnd
Isw
-
0.3
1
A
Vsw (differential)= -60V to +270V
-40oC
Vsw (differential)= -310V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +250V
DC Current Limit
+25oC
Vsw (on) = +/- 10V
Isw
-
120
-
mA
+85oC
Vsw (on) = +/- 10V
Isw
-
80
-
mA
-40oC
Vsw (on) = +/- 10V
Isw
-
210
-
mA
Dynamic Current Limit:
Break switches in ON state, Ringing
Isw
-
2.5
-
A
(t=<0.5
s)
access switches OFF, Apply +/- 1000V
at 10/1000
s pulse, Appropriate
secondary protection in place.
RDS
ON
+25C
Isw (on) = +/-0mA, +/-10mA
V
-
60
-
+85C
Isw (on) = +/-0mA, +/-10mA
V
-
85
100
-40C
Isw (on) = +/-0mA, +/-10mA
V
-
45
-
Logic Input to Switch Output Isolation:
+25oC
Vsw (T
RING
, T
LINE
) = +/-320V
Isw
-
0.1
1
A
Logic Inputs = Gnd
+85oC
Vsw (T
RING
, T
LINE
) = +/-330V
Isw
-
0.3
1
A
Logic Inputs = Gnd
-40oC
Vsw (T
RING
, T
LINE
) = +/-310V
Isw
-
0.1
1
A
Logic Inputs = Gnd
Table 3. Ringing Access Switch, SW4
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current
+25oC
Vsw (differential)= -255V to +210V
Isw
-
.05
1
A
Vswitch (differential)= +255V to -210V
+85oC
Vsw (differential)= -270V to +210V
Isw
-
0.1
1
A
Vsw (differential)= +270V to -210V
-40oC
Vsw (differential)= -245V to +210V
Isw
-
.05
1
A
Vsw (differential)= +245V to -210V
ON Voltage
Isw (on) = +/- 1mA
-
-
1.5
3
V
Ring Generator Current
Vcc = 5V, IN
TESTin
= 0
IR
-
0.1
0.25
mA
During Ring
IN
TESTout
= 0
Surge Current
-
-
-
-
2
A
Release Current
-
-
-
450
-
A
ON-resistance
Isw (on) = +/-70mA, +/-80mA
V
-
8.5
12
Logic Input to Switch Output Isolation:
+25oC
Vsw (R
RING
, R
LINE
) = +/-320V
Isw
-
.05
1
A
Logic Inputs = Gnd
+85oC
Vsw (R
RING
, R
LINE
) = +/-330V
Isw
-
0.1
1
A
Logic Inputs = Gnd
-40oC
Vsw (R
RING
, R
LINE
) = +/-310V
Isw
-
.05
1
A
Logic Inputs = Gnd
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Rev. E
CPC7583
Table 4. Loop Access Switches, SW5 and SW6
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
+25oC
Vsw (differential) = -320V to +Gnd
Isw
-
0.1
1
A
Vsw (differential) = -60V to +260V
+85oC
Vsw (differential) = -330V to Gnd
Isw
-
0.3
1
A
Vsw (differential) = -60V to +270V
-40oC
Vsw (differential) = -310V to +Gnd
Isw
-
0.1
1
A
Vsw (differential) = -60V to +250V
RDSON:
+25oC
Isw (on) = +/-5mA, +/-10mA
V
-
35
-
+85oC
Isw (on) = +/-5mA, +/-10mA
V
-
50
70
-40oC
Isw (on) = +/-5mA, +/-10mA
V
-
26
-
DC Current Limit:
+25oC
Vsw (on) = +/-10V
Isw
140
-
mA
+85oC
Vsw (on) = +/-10V
Isw
80
100 -
mA
-40oC
Vsw (on) = +/-10V
Isw
-
210 250 mA
Dynamic Current LImit Break switches in ON state; ringing
Isw
-
2.5
-
A
(t=<0.5
s)
access switches OFF; apply +/-1000V at
10/1000
s pulse; appropriate secondary
protection in place.
Logic Input to Switch Output Isolation:
+25oC
Vsw (T
TESTout
, T
LINE,
R
TESTout
, R
LINE
) = +/-320V
Isw
-
0.1
1
A
Logic Inputs = Gnd
+85oC
Vsw (T
TESTout
, T
LINE,
R
TESTout
, R
LINE
) = +/-330V
Isw
-
0.3
1
A
Logic Inputs = Gnd
-40oC
Vsw (T
TESTout
, T
LINE,
R
TESTout
, R
LINE
) = +/-310V
Isw
-
0.1
1
A
Logic Inputs = Gnd
Table 5. Ringing Test Return Switch SW7
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
+25oC
Vsw (differential)= -320V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +260V
+85oC
Vsw (differential)= -330V to Gnd
Isw
-
0.3
1
A
Vsw (differential)= -60V to +270V
-40oC
Vsw (differential)= -310 to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +250V
RDS
ON
+25C
Isw (on) = +/-0mA, +/-10mA
V
-
60
-
+85C
Isw (on) = +/-0mA, +/-10mA
V
-
85
100
-40C
Isw (on) = +/-0mA, +/-10mA
V
-
45
-
DC Current Limit
+25oC
Vsw (on) = +/- 10V
Isw
-
120
-
mA
+85oC
Vsw (on) = +/- 10V
Isw
-
80
-
mA
-40oC
Vsw (on) = +/- 10V
Isw
-
210
-
mA
Logic Input to Switch Output Isolation:
+25oC
Vsw (T
RING
, T
TESTin
) = +/-320V
Isw
-
0.1
1
A
Logic Inputs = Gnd
+85oC
Vsw (T
RING
, T
TESTin
) = +/-330V
Isw
-
0.3
1
A
Logic Inputs = Gnd
-40oC
Vsw (T
RING
, T
TESTin
) = +/-310V
Isw
-
0.1
1
A
Logic Inputs = Gnd
CPC7583
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Rev. E
Table 6. Ringing Test Switch SW8
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
+25oC
Vsw (differential)= -60V to +175V
Isw
-
.05
1
A
Vsw (differential)= +60V to -175V
+85oC
Vsw (differential)= -60V to +175V
Isw
-
0.1
1
A
Vsw (differential)= +60V to -175V
-40oC
Vsw (differential)= -60V to +175V
Isw
-
.05
1
A
Vsw (differential)= +60V to -175V
ON-resistance
Isw (on) = +/-70 mA, +/-80mA
V - 6 20
ON- voltage
Isw (on) = +/-1mA
-
-
0.75
1.5
V
Release Current
-
-
-
450
-
A
Logic Input to Switch Output Isolation:
+25oC
Vsw (R
RING
, R
TESTin
) = +/-320V
Isw
-
.05
1
A
Logic Inputs = Gnd
+85oC
Vsw (R
RING
, R
TESTin
) = +/-330V
Isw
-
0.1
1
A
Logic Inputs = Gnd
-40oC
Vsw (R
RING
, R
TESTin
) = +/-310V
Isw
-
.05
1
A
Logic Inputs = Gnd
*
Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.
Table 7. Test in Switches, SW9 and SW10
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
+25oC
Vsw (differential)= -320V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +260V
+85oC
Vsw (differential)= -330V to Gnd
Isw
-
0.3
1
A
Vsw (differential)= -60V to +270V
-40oC
Vsw (differential)= -310V to Gnd
Isw
-
0.1
1
A
Vsw (differential)= -60V to +250V
RDSON
:
+25oC
Isw(on) = +/-5 mA, +/-10mA
V
-
35
-
+85oC
Isw(on) = +/-5 mA, +/-10mA
V
-
50
70
-40oC
Isw(on) = +/-5 mA, +/-10mA
V
-
26
-
DC Current Limit:
+25oC
Vsw (On) = +/-10V
Isw
-
160
-
mA
+85oC
Vsw (On) = +/-10V
Isw
80
110
-
mA
-40oC
Vsw (On) = +/-10V
Isw
-
210
250
mA
Logic Input to Switch Output Isolation:
+25oC
Vsw (T
TESTin
, R
TESTin
) = +/-320V
Isw
-
0.1
1
A
Logic Inputs = Gnd
+85oC
Vsw (T
TESTin
, R
TESTin
) = +/-330V
Isw
-
0.3
1
A
Logic Inputs = Gnd
-40oC
Vsw (T
TESTin
, R
TESTin
) = +/-310V
Isw
-
0.1
1
A
Logic Inputs = Gnd
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Rev. E
CPC7583
Table 8. Additional Electrical Characteristics
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Digital Input Characteristics
Input Low Voltage
-
-
-
-
1.5
V
Input High Voltage
-
-
3.5
-
-
V
Input Leakage Current (High)
VDD = 5.5V, VBAT = -75V,
Ilog
-
0.1
1
A
Vlog = 5V
Input Leakage Current (Low)
VDD = 5.5V, VBAT = -75V,
Ilog
-
0.1
1
A
Vlog = 0V
Power Requirements
Power Dissipation
VDD = 5V, VBAT = -48V,
Idle/Talk State or All Off State
IDD, IBAT
-
5.0
7.5
mW
Ringing State or Test State
IDD
-
6.0
10
mW
VDD Current
VDD = 5V,
Idle/Talk State or All Off State
IDD
-
1.0
1.5
mA
Ringing State or Test State
IDD
-
1.2
1.9
mA
VBAT Current
VBAT = -48V,
Idle/Talk State or All Off State
IBAT
-
4
10
A
Ringing State or Test State
IBAT
-
4
10
A
Temperature Shutdown Requirements
1
Shutdown Activation Temperature
-
-
110
125
150
oC
Shutdown Circuit Hysteresis
-
-
10
-
25
oC
1
Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state.
Table 9. Make-Before-Break Operation (Ringing to Idle/Talk Transition)
Ring
Ring
Break
Return
Access
All Other
Switches
Switch
Switch
Test
Ring
Testin
Testout
TSD
State
Timing
1 & 2
3
4
Switches
5V
0V 0V Float Ringing -
Open Closed Closed
Open
0V 0V 0V Float Make-before-break
SW4 waiting for next zero current Closed Open
Closed
Open
crossing to turn off. Maximum
time is half of ringing. In this
transition state, current that is
limited to the dc break switch
current limit value will be sourced
from the ring node of the SLIC
0V 0V 0V Float Idle / Talk
Zero cross current has occurred Closed Open Open
Open
CPC7583
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7
Rev. E
Table 10. Break-Before-Make Operation (Ringing to Idle/Talk Transition)
Ring
Ring
Break
Return
Access
All Other
Switches
Switch
Switch
Access
Ring
Testin
Testout TSD
State
Timing
1 & 2
3
4
Switches
5V 0V 0V Float Ringing - Open Closed Closed Open
5V 0V 5V Float All Off
Hold this state for </= 25ms. Open Open Closed Open
SW4 waiting for zero current to
turn off.
5V
0V 5V Float All Off
Zero current has occurred. Open Open Open Open
SW4 has opened.
0V 0V 0V Float Idle/Talk
Release Break Switches Closed Open Open Open
Alternate "Break-Before-Make" Operation
Note that the break-before-make operation can also be achieved using TSD as an input. In lines 2 & 3 of Table 10, instead of using the
logic input pins to force the "all off" state, force TSD to ground. This will override the logic inputs and also force the all off state. Hold
this state for 25 ms. During this 25 ms all off state, toggle the inputs from the 10 (ringing state) to 00 (idle/talk state). After 25 ms,
release TSD to return switch control to the input pins which will set the idle talk state.
When using the CPC7583 in this mode, forcing TSD to ground will override the INPUT pins and force an all off state. Setting TSD to
+5V will allow switch control via the logic INPUT pins. However, setting TSD to +5V will also disable the thermal shutdown mecha-
nism. This is not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float.
Thus when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float
(allows switch control via logic input pins and thermal shutdown mechanism is active). This may require use of an open collector
buffer.
Table 11. Electrical Specifications, Protection Circuitry
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Parameters Related to Diodes
(in Diode Bridge)
Voltage Drop @ Continuous
Apply +/-dc current limit of break
Forward
-
2.8
3.5
V
Current (50/60 Hz)
switches
Voltage
Voltage Drop @ Surge
Apply +/-dynamic current limit of
Forward
-
5
-
V
Current
break swithces
Voltage
Parameters Related to
Protection SCR
1
Surge Current
-
-
-
-
*
A
Trigger Current (25C)
-
I
TRIG
-
60
-
mA
Hold Current (25C)
-
I
HOLD
-
110
-
mA
Trigger Current (85C)
-
I
TRIG
-
35
-
mA
Hold Current (85C)
-
I
HOLD
60
70
-
mA
Gate Trigger Voltage
Trigger Current
-
V
BAT
- 4
-
V
BAT
- 2
V
Reverse Leakage Current
VBAT
-
-
-
1.0
A
ON State Voltage
1
0.5A t = 0.5 ms
V
on
-
-3
-
V
2.0A t = 0.5 ms
-
-
-5
-
V
1
Only for the CPC7583BA and CPC7583BC.
* Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
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8
Rev. E
CPC7583
Table 12. Truth Table for the CPC7583BA and CPC7583BB
INring
INtestin
INtestout
TSD
TESTin
Break
RingTest
Ring
TESTout
Switches
Switches
Switches
Switches
Switches
0V
0V
0V
5V/Float
1
Off
On
Off
Off
Off
3
0V
0V
5V
5V/Float
1
Off
Off
Off
Off
On
4
0V
5V
0V
5V/Float
1
On
Off
Off
Off
Off
5
5V
0V
0V
5V/Float
1
Off
Off
Off
On
Off
6
5V
5V
0V
5V/Float
1
Off
Off
On
Off
Off
7
0V
5V
5V
5V/Float
1
On
Off
Off
Off
On
8
5V
0V
5V
5V/Float
1
Off Off Off Off
Off
9
5V
5V
5V
5V/Float
1
Off
Off
Off
Off
Off
9
Don't
Don't
Don't
0V
2
Off
Off
Off
Off
Off
9
Care Care Care
1
If TSD = 5V, the thermal shutdown mechanism is disabled.
If TSD if floating, the thermal shutdown mechanism is active.
2
Forcing TSD to ground overrides the logic input pins and forces an all off state.
3
Idle/Talk State.
4
TESTout state.
5
TESTin state.
6
Power Ringing State.
7
Ringing generator test state.
8
Simultaneous TESTout and TESTin state.
9
All OFF State
A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin
LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state
control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data
latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The
state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic
0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT
and LATCH.
CPC7583
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9
Rev. E
Table 13. Truth Table for the CPC7583BC and CPC7583BD
INring
INtestin
INtestout
TSD
TESTin
Break
RingTest
Ring
TESTout
Switches
Switches
Switches
Switches
Switches
0V
0V
0V
5V/Float
1
Off
On
Off
Off
Off
3
0V
0V
5V
5V/Float
1
Off
Off
Off
Off
On
4
0V
5V
0V
5V/Float
1
On
Off
Off
Off
Off
5
5V
0V
0V
5V/Float
1
Off
Off
Off
On
Off
6
5V
5V
0V
5V/Float
1
Off
Off
On
Off
Off
7
0V
5V
5V
5V/Float
1
On
Off
Off
Off
On
8
5V
0V
5V
5V/Float
1
Off Off Off Off
Off
9
5V
5V
5V
5V/Float
1
Off
Off
On
Off
On
10
Don't
Don't
Don't
0V
2
Off
Off
Off
Off
Off
9
Care Care Care
1
If TSD = 5V, the thermal shutdown mechanism is disabled.
If TSD if floating, the thermal shutdown mechanism is active.
2
Forcing TSD to ground overrides the logic input pins and forces an all off state.
3
Idle/Talk State.
4
TESTout state.
5
TESTin state.
6
Power Ringing State.
7
Ringing generator test state.
8
Simultaneous TESTout and TESTin state.
9
All OFF State
10
Simultaneous TESTout - Ring Test state.
A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin
LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state
control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data
latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The
state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic
0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT
and LATCH.
www.clare.com
10
Rev. E
CPC7583
SOG
Symbol
Description
1
F
GND
Fault ground.
2
NC
No Connection.
3
NC
No Connection.
4
NC
No Connection.
5
T
TESTin
Test (in) access on TIP.
6
T
BAT
Connect to TIP on SLIC side.
7
T
LINE
Connect to TIP on line side.
8
T
RING
Connect to return ground for ringing generator.
9
NC
No connection.
10
T
TESTout
Test (out) access on TIP.
11
NC
No connection.
12
V
DD
5V supply
13
T
SD
Temperature shutdown pin. Can be used as a logic
level input or an output. See Tables 9, 10, 12 and13 for
more details. As an output, will read 5V when the
device is in its operational mod and 0V in the thermal
shutdown mode. To disable the thermal shutdown mode
mechanism, tie this pin to 5V (not recommended).
14
D
GND
Digital ground
15
IN
TESTout
Logic level switch input control.
16
IN
RING
Logic level switch input control.
17
IN
TESTin
Logic level switch input control.
18
LATCH
Data input control, active-high, transparent low.
19
R
TESTout
Test (out) access on RING.
20
R
RING
Connect to ringing generator.
21
NC
No connection.
22
R
LINE
Connect to RING on line side.
23
R
BAT
Connect to RING on SLIC side.
24
R
TESTin
Test (in) access on RING.
25
NC
No connection.
26
NC
No connection.
27
NC
No connection
28
V
BAT
Battery voltage. Used as a reference for protection circuit.
Package Pinout
* Only the CPC7583BA and CPC7583BC
contain the protection SCR
CPC7583
T
BAT
SW1
SW5
SW9
SW2
SW8
SW10
Control
Logic
F
GND
D
GND
T
TESTin
IN
TESTin
R
T
TESTout
IN
TESTout
R
TESTout
T
LINE
T
RING
V
DD
T
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD
V
BAT
R
BAT
R
LINE
R
RING
LATCH
IN
RING
27
26
25
24
23
22
21
20
SW7
SW6
19
18
17
16
15
28
1
3
4
5
6
7
8
2
9
10
11
12
13
14
SW3
SW4
SCR and
TRIP CKT
CPC7583
www.clare.com
11
Rev. E
Functional Description
Introduction
The CPC7583 has eight distinct states. Please consult the
truth tables in table 12 and 13 for version differences.
Idle/talk state (line break switches SW1, and SW2
closed). All other switches open.
Ringing state, (ringing switches SW3, SW4 closed).
All other switches open.
Loop access (loop access switches SW5, SW6
closed). All other switches open.
Ring generator test state (SW7, SW8 closed). All
other switches open.
SLIC test state Testin switches closed (SW9, SW10).
Simultaneous Loop and SLIC access state. (SW9,
SW10, SW5 and SW6 closed). All other switches open.
Simultaneous test out and ring test (SW5, SW6,
SW7, SW8 closed). All other switches open on the "BC"
abd "BD" version.
All Off state (all switches open).
The CPC7583 offers break-before-make and make-before-
break switching with simple logic level input control. Solid
state switch construction means no impulse noise is gen-
erated when switching during ring cadence or ring trip, thus
eliminating the need for external "zero cross" switching cir-
cuitry. State control is via logic level input so no additional
driver circuitry is required. The line break switches SW1
and SW2 are linear switches that have exceptionally low
RDS
ON
and excellent matching characteristics. The ring-
ing access switch SW4 has a breakdown voltage rating of
>480V which is sufficiently high, with proper protection, to
prevent breakdown in the presence of a transient fault con-
dition. (i.e., passing the transient on to the ring generator)
Integrated into the CPC7583 is a diode bridge clamping
circuit, current limiting and thermal shutdown mechanism
to provide protection to the SLIC device during a fault con-
dition. Positive and negative surges are reduced by the
current limiting circuitry and steered to ground via diodes.
Power cross transients are also reduced by the current lim-
iting and thermal shutdown circuits.
To protect the CPC7583 from an overvoltage fault condi-
tion, use of a secondary protector is required. The sec-
ondary protector must limit the voltage seen at the tip and
ring terminals to a level below the max breakdown volt-
age of the switches. To minimize the stress on the solid-
state contacts, use of a foldback or crowbar type sec-
ondary protector is recommended. With proper selection
of the secondary protector, a line card using the CPC7583
will meet all relevant ITU, LSSGR, FCC or UL protection
requirements.
The CPC7583 operates from a +5V supply only. This gives
the device extremely low idle and active power dissipation
and allows use with virtually any range of battery voltage.
A battery voltage is also used by the CP7583 as a refer-
ence for the integrated protection circuit. In the event of a
loss of battery voltage, the CPC7583 will enter an "all off"
state.
Switch Timing
The CPC7583 provides, when switching from the ringing
state to the idle/talk state, the ability to control the timing
when the ringing access switches SW3 and SW4 are re-
leased relative to the state of the line break switches SW1
and SW2 using simple logic level input. This is referred to
as a "make before break" or "break before make" opera-
tion. When the line break switch contacts (SW1, SW2) are
closed (or made) before the ringing access switch contact
(SW3, SW4) is opened (or broken), this is referred to a
`make-before-break' operation. Break-before-make opera-
tion occurs when the ringing access contact (SW3, SW4)
is opened (broken) before the line break switch contacts
(SW1, SW2) are closed (made). With the CPC7583 the
"make before break" and "break before make" operations
can easily be selected by applying logic level inputs to
IN
TESTout,
IN
RING
and IN
TESTin
of the device.
The logic sequences for either mode of operation are given
in Tables 9 and 10. Logic states and explanations are given
in Tables 12 and 13.
Break-before make operation can also be achieved using
pin 13 (TSD) as an input. In table 10 lines 2 and 3 it is
possible to induce the switches to "all off" by grounding pin
13 (TSD) instead of apply logic input to the pins. This has
the effect of overriding the logic inputs and forcing the de-
vice to the "all off" state. Hold this input state for 25ms.
During this hold period, toggle the inputs from the ringing
state to the idle/talk state. After the 25ms release pin 13
(TSD) to return the switch control to the input IN
TESTout,
IN
RING,
IN
TESTin
and reset the device to the idle/talk state.
Setting pin 13 (TSD) to +5V will allow switch control using
the logic inputs. This setting, however, will also disable the
thermal shutdown circuit and is therefore not recommended.
When using logic controls via the input pins (IN
TESTout,
IN
RING
and IN
TESTin
), pin 13 (TSD) should be allowed to float. As a
result the two recommended states when using pin 13
www.clare.com
12
Rev. E
CPC7583
(TSD) as a control are 0 which forces the device to the "all
off state" or float which allow logic inputs to remain active.
This may require use of an open collector buffer.
Ring Access Switch Zero Cross Current Turn Off
After the application of a logic input to turn SW4 off, the
ring access switch is designed to delay the change in state
until the next zero crossing. Once on, the switch requires a
zero current cross to turn off and therefore should not be
used to switch a pure DC signal. The switch will remain in
the on state no matter what logic input until the next zero
crossing. These switching characteristics will reduce and
possibly eliminate overall system impulse noise normally
associated with ringing access switches. The attributes of
ringing access switch may make it possible to eliminate
the need for a zero cross switching scheme. A minimum
impedance of 300
in series with the ring generator is
recommended.
Power Supplies
Both a +5V supply and battery voltage are connected to
the CPC7583. CPC7583 switch state control is powered
exclusively by the +5V supply. As a result, the CPC7583
exhibits extremely low power dissipation during both active
and idle states.
Battery Voltage Monitor
The CPC7583 also uses the voltage reference to monitor
battery voltage. If battery voltage is lost, the CPC7583 will
immediately enter the "all off" state and remain in this state
until the battery voltage is restored. The device will also
enter the "all off" state if the battery voltage rises above
10V and will remain there until the battery voltage drops
below 15V. This battery monitor feature draws a small
current from the battery (<1
A) and will add slightly to the
device's overall power dissipation.
Protection
Diode Bridge/SCR
The CPC7583 uses a combination of current limited break
switches, a diode bridge/SCR clamping circuit and a ther-
mal shutdown mechanism to protect the SLIC device or
other associated circuitry from damage during line tran-
sient events such as lightning. During a positive transient
condition, the fault current is conducted through the diode
bridge and to ground. During a negative transient of two or
four volts more negative than the battery, the SCR con-
ducts and faults are shunted to ground via the SCR and
diode bridge.
Also, in order for the SCR to crowbar or foldback, the on
voltage (see Table 11) of the SCR must be less negative
than the battery reference voltage. If the battery voltage is
less negative the SCR on voltage, the SCR will not crow-
bar, however it will conduct fault currents to ground.
For power induction or power cross fault conditions, the
positive cycle of the transient is clamped to the diode drop
above ground and the fault current directed to ground. The
negative cycle of the transient will cause the SCR to con-
duct when the voltage exceeds the battery reference volt-
age by two to four volts, steering the current to ground.
Current Limiting function
If a lightning strike transient occurs when the device in the
talk/idle state, the current is passed along the line to the
integrated protection circuitry and limited by the dynamic
current limit response of break switches SW1 and SW2.
When a 1000V 10x1000 pulse (LSSGR lightning) is ap-
plied to the line though a properly clamped external pro-
tector, the current seen at pins 6 (T
BAT
) and pin 23 (R
BAT
) will
be a pulse with a typical magnitude and duration of 2.5A
and < 0.5ms.
If a power cross fault occurs with device in the talk/idle
state, the current is passed though the break switches SW1
and SW2 on to the integrated protection circuit and is lim-
ited by the dynamic DC current limit response of the two
break switches. The DC current limit, specified over tem-
perature, is between 80mA and 400mA and the circuitry
has a negative temperature coefficient. As a result, if the
device is subjected to extended heating due to power cross
fault, the measured current at pin 6 (T
BAT
) and pin 23 (R
BAT
)
will decrease as the device temperature increases. If the
device temperature rises sufficiently, the temperature shut-
down mechanism will activate and the device will default to
the "all off" state.
Temperature Shutdown
The thermal shutdown mechanism will activate when the
device temperature reaches a minimum of 110
C placing
the device in the "all off" state regardless of logic input.
During this thermal shutdown mode, pin 13 (TSD) will read
0V. Normal output of TSD is +V
DD
.
If presented with a short duration transient such as a light-
ning event, the thermal shutdown feature will not typically
activate. But in an extended power cross transient, the
device temperature will rise and the thermal shutdown will
activate forcing the switches to an "all off" state. At this
point the current measured at pin 6 (T
BAT
) and pin 23 (R
BAT
)
will drop to zero. Once the device enters thermal shut-
down it will remain in the "all off" state until the temperature
of the device drops below the activation level of the ther-
mal shutdown circuit. This will return the device to the state
prior to thermal shutdown. If the transient has not passed,
current will flow at the value allowed by the dynamic DC
current limiting of the switches and heating will begin again,
reactivating the thermal shutdown mechanism. This cycle
CPC7583
www.clare.com
13
Rev. E
of entering and exiting the thermal shutdown mode will
continue as long as the fault condition persists. If the mag-
nitude of the fault condition is great enough, the external
secondary protector could activate and shunt all current to
ground.
The thermal shutdown mechanism of the CPC7583 can
be disable by applying +V
DD
to pin 13 (TSD)
External Protection Elements
The CPC7583 requires only one overvoltage secondary pro-
tector on the loop side of the device. The integrated protec-
tion feature described above negates the need for protection
on the line side. The purpose of the secondary protector is to
limit voltage transients to levels that do not exceed the break-
down voltage or input-output isolation barrier of the CPC7583.
A foldback or crowbar type protector is recommended to mini-
mize stresses on the device.
Consult Clare's app note, AN-100, "Designing Surge and
Power Fault Protection Circuits for Solid State Subscriber
Line Interfaces" for equations related to the specifications
of external secondary protectors, fused resistors, and PTCs.
Data Latch
The CPC7583 has an integrated data latch. The latch op-
eration is controlled by logic level input pin 18 (LATCH).
The data input of the latch is pin 15 (IN
TESTout
), pin 16 (IN
RING
)
and pin 17 (IN
TESTin
) of the device while the output of the
data latch is an internal node used for state control. When
LATCH control pin is at logic 0, the data latch is transpar-
ent and data control signals flow directly through to state
control. A change in input will be reflected in a change is
switch state. When LATCH control pin is at logic 1, the
data latch is now active and a change in input control will
not affect switch state. The switches will remain in the po-
sition they were in when the LATCH changed from logic 0
to logic 1 and will not respond to changes in input as long
as the latch is at logic 1. In addition, TSD input is not tied
to the data latch. Therefore, TSD is not affected by the
LATCH input and TSD input will override state control via
pin 15 (IN
TESTout
), pin 16 (IN
RING
) and pin 17 (IN
TESTin
) and
the LATCH.
www.clare.com
14
Rev. E
CPC7583
Dimensions
mm
(Inches)
Mechanical Dimensions
28 Pin SOIC
1.27 Typ
(.050 Typ)
2.54+/-.127
(.100+/-.005)
7.468+/-.127
(.294+/-.005)
10.312+/-.051
(.406+/-.003)
.250 Typ
(.010 Typ)
.813+/-.102
(.032+/-.004)
3 - 7
o
o
18.034+/-.127
(.710+/-.005)
.330 x 45 MAX
(.013 x 45 MAX)
o
o
CPC7583
www.clare.com
15
Rev. E
Notes:
CLARE LOCATIONS
Clare Headquarters
78 Cherry Hill Drive
Beverly, MA 01915
Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
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145 Columbia
Aliso Viejo, CA 92656-1490
Tel: 1-949-831-4622
Fax: 1-949-831-4628
Clare Switch Division
4315 N. Earth city Expressway
Earth City, MO 63045
Tel: 1-314-770-1832
Fax: 1-314-770-1812
SALES OFFICES
AMERICAS
Americas Headquarters
Clare
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Tel: 1-978-524-6700
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Mahwah, NJ 07430
Tel: 1-201-236-0101
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Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
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1852 West 11th Street, #348
Tracy, CA 95376
Tel: 1-209-832-4367
Fax: 1-209-832-4732
Toll Free: 1-800-27-CLARE
Canada
Clare Canada Ltd.
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
EUROPE
European Headquarters
CP Clare nv
Bampslaan 17
B-3500 Hasselt (Belgium)
Tel: 32-11-300868
Fax: 32-11-300890
France
Clare France Sales
Lead Rep
99 route de Versailles
91160 Champlan
France
Tel: 33 1 69 79 93 50
Fax: 33 1 69 79 93 59
Germany
Clare Germany Sales
ActiveComp Electronic GmbH
Mitterstrasse 12
85077 Manching
Germany
Tel: 49 8459 3214 10
Fax: 49 8459 3214 29
Italy
C.L.A.R.E.s.a.s.
Via C. Colombo 10/A
I-20066 Melzo (Milano)
Tel: 39-02-95737160
Fax: 39-02-95738829
Sweden
Clare Sales
Comptronic AB
Box 167
S-16329 Spnga
Tel: 46-862-10370
Fax: 46-862-10371
United Kingdom
Clare UK Sales
Marco Polo House
Cook Way
Bindon Road
Taunton
UK-Somerset TA2 6BG
Tel: 44-1-823 352541
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ASIA PACIFIC
Asian Headquarters
Clare
Room N1016, Chia-Hsin, Bldg II,
10F, No. 96, Sec. 2
Chung Shan North Road
Taipei, Taiwan R.O.C.
Tel: 886-2-2523-6368
Fax: 886-2-2523-6369
http://www.clare.com
Specification: DS-CPC7583-RE
Copyright 2001, Clare, Inc.
All rights reserved. Printed in USA.
8/1/01
Worldwide Sales Offices
Clare cannot assume responsibility for use of any circuitry other
than circuitry entirely embodied in this Clare product. No circuit
patent licenses nor indemnity are expressed or implied. Clare
reserves the right to change the specification and circuitry, with-
out notice at any time. The products described in this document
are not intended for use in medical implantation or other direct
life support applications where malfunction may result in direct
physical harm, injury or death to a person.
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