DS-CPC7583 - R3.0
www.clare.com
1
Features
Small 20 pin or 28 pin SOIC or 28 pin
micro-leadframe (MLP) package
MLP version provides 65% PCB area reduction over
4
th
generation EMRs
Monolithic IC reliability
Low, matched, R
ON
Eliminates the need for zero-cross switching
Flexible switch timing for transition from ringing
mode to talk mode.
Clean, bounce-free switching
SLIC tertiary protection via integrated current
limiting, voltage clamping and thermal shutdown
5 V operation with power consumption < 10.5 mW
Intelligent battery monitor
Logic-level inputs, no external drive circuitry required
SOIC versions pin-compatible with Legerity
7583/8583 family
Applications
Central office (CO)
Digital Loop Carrier (DLC)
PBX Systems
Digitally Added Main Line (DAML)
Hybrid Fiber Coax (HFC)
Fiber in the Loop (FITL)
Pair Gain System
Channel Banks
Description
The CPC7583 is a monolithic 10-pole line card access
switch in a 20 or 28 pin SOIC or a 28 pin MLP
package. It provides the necessary functions to
replace three 2-Form-C electromechanical relays on
analog line cards and combined voice and data line
cards found in central office, access, and PBX
equipment. The device contains solid state switches
for tip and ring line break, ringing injection/ringing
return, and test access. The CPC7583 requires only a
+5 V supply and offers break-before-make or
make-before-break switch operation using simple
logic-level input control.
Ordering Information
Specify CPC7583Zx for 20 pin SOIC package,
CPC7583Bx for 28 pin SOIC package, or CPC7583Mx
for MLP package in tubes. Add -TR to the part number
for tape and reel packaging.
Part Number
Description
CPC7583xA
With protection SCR
CPC7583xB
Without protection SCR
CPC7583xC
With extra logic state and protection SCR
CPC7583xD
With extra logic state but without protection
SCR
CPC7583
T
LINE
R
LINE
T
BAT
V
DD
R
BAT
D
GND
V
BAT
F
GND
V
REF
IN
TESTIN
IN
RINGING
IN
TESTOUT
T
SD
LATCH
7
10
8
5
22
6
12
13
14
28
1
24
20
19
23
17
16
15
18
L
A
T
C
H
Switch
Control
Logic
SCR
and
Trip
Circuit
+5 Vdc
SLIC
Secondary
Protection
X
X
X
X
X
X
X
X
X
SW5
SW7
SW6
SW2
SW4
SW10
SW8
T
TESTIN
(T
)
CHANTEST
T
TESTOUT
(T
)
DROPTEST
R
TESTOUT
(R
)
DROPTEST
R
TESTIN
(R
)
CHANTEST
T
RING
SW3
SW9
SW1
300
(min.)
RINGING
V
BAT
X
Tip
Ring
NOTE: Pin assignments are for 28 pin device.
CPC7583
Line Card Access Switch
CPC7583
2
www.clare.com
R3.0
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.5 TEST
OUT
Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.6 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.7 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.8 TEST
In
Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7.1 Truth Table for CPC7583xA and CPC7583xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7.2 Truth Table for CPC7583xC and CPC7583xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 T
SD
Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 CPC7583Z - 20 Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 CPC7583B - 28 Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 CPC7583M - 28 Pin MLP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.4 CPC7583Z - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.5 CPC7583B - Tape and Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.6 CPC7583M - Tape and Reel Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CPC7583
R3.0
www.clare.com
3
1. Specifications
1.1 Package Pinout
1.2 Pinout Description
CPC7583B &
CPC7583M
T
BAT
F
GND
D
GND
T
TESTin
IN
TESTin
R
T
TESTout
IN
TESTout
R
TESTout
T
LINE
T
RINGING
V
DD
T
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD
V
BAT
R
BAT
TESTin
R
LINE
R
RINGING
LATCH
IN
RINGING
27
26
25
24
23
22
21
20
19
18
17
16
15
28
1
3
4
5
6
7
8
2
9
10
11
12
13
14
CPC7583Z
IN
TESTIN
R
TESTIN
IN
TESTOUT
R
TESTOUT
V
BAT
R
BAT
R
LINE
R
RINGING
LATCH
IN
RINGING
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
T
BAT
F
GND
D
GND
T
TESTIN
T
LINE
V
DD
T
SD
NC
T
TESTOUT
T
RINGING
20
Pin
28
Pin
Name
Description
1
1
F
GND
Fault ground
2
NC
No connection
3
NC
No connection
4
NC
No connection
2
5
T
TESTin
Connect to TEST
IN
bus tip lead
3
6
T
BAT
Connect to tip on SLIC side
4
7
T
LINE
Connect to tip on line side
5
8
T
RINGING
Connect to ringing generator return
9
NC
Not connected
6
10
T
TESTout
Connect to TEST
OUT
bus tip lead
7
11
NC
No connection
8
12
V
DD
+5 V supply
9
13
T
SD
Temperature shutdown pin. Bi-directional
I/O with internal pullup to V
DD
. Output
function indicates status of thermal
shutdown circuitry. Input function can be
used to set the `all off' mode using an
open-drain type output.
10 14
D
GND
Digital ground
11 15
IN
TESTout
Logic-level switch control input
12 16 IN
RINGING
Logic-level switch control input
13 17
IN
TESTin
Logic-level switch control input
14 18
LATCH
Data latch control, active high, transparent
low
15 19
R
TESTout
Connect to TEST
OUT
bus ring lead
16 20
R
RINGING
Connect to ringing generator current
limiting resistor
21
NC
No connection
17 22
R
LINE
Connect to ring on the line side
18 23
R
BAT
Connect to ring on the SLIC side
19 24
R
TESTin
Connect to TEST
IN
bus ring lead
25
NC
No connection
26
NC
No connection
27
NC
No connection
20 28
V
BAT
Battery voltage supply. Must be capable of
sourcing the trigger current for proper
operation of the SCR.
CPC7583
4
www.clare.com
R3.0
1.3 Absolute Maximum Ratings (at 25 C)
1.4 Electrical Characteristics, T
A
= -40 C to +85 C
Unless otherwise specified, minimum and maximum
values are production testing requirements. Typical
values are characteristic of the device and are the
result of engineering evaluations. Typical values are
provided for information purposes only and are not
part of the testing requirements. V
DD
= 5V
dc
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
1.4.1 Power Supply Specifications
1.4.2 Break Switches, SW1 and SW2
Parameter
Minimum Maximum
Unit
Operating temperature
-40
+110
C
Storage temperature
-40
+150
C
Operating relative humidity
5
95
%
Pin soldering temperature
(10 seconds max)
-
+260
C
+5 V power supply(V
DD
)
-0.3
7
V
Battery Supply
-
-85
V
D
GND
to F
GND
separation
-5
+5
V
Logic input voltage
-0.3
V
DD
+0.3
V
Logic input to switch output
isolation
-
330
V
Switch open contact
isolation (SW1, SW2, SW3,
SW5, SW6, SW7, SW9,
SW10)
-
330
V
Switch open contact
isolation (SW4)
-
465
V
Switch open contact
isolation (SW8)
-
235
V
Supply
Minimum Typical Maximum
Unit
V
DD
+4.5
+5.0
+5.5
V
V
BAT
1
-19
-
-72
V
1
V
BAT
is used only for internal protection circuitry. If V
BAT
rises above
-10 V, the device will enter the all-off state and will remain in the all-off state
until the battery drops below -15 V.
ESD Rating (Human Body Model)
1000 V
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -320 V to gnd
V
SW
(differential) = +260 V to -60 V
I
SW
-
0.1
1
A
+85 C
V
SW
(differential) = -330 V to gnd
V
SW
(differential) = +270 V to -60 V
0.3
-40 C
V
SW
(differential) = -310 V to gnd
V
SW
(differential) = +250 V to -60 V
0.1
R
ON
+25 C
I
SW
(on) = 10 mA, 40 mA,
R
BAT
and T
BAT
= -2 V
R
ON
-
14.5
-
+85 C
20.5
28
-40 C
10.5
-
R
ON
match
Per on-resistance test condition of SW1
& SW2
R
ON
0.15
0.8
CPC7583
R3.0
www.clare.com
5
1.4.3 Ringing Return Switch, SW3
DC current limit
+25 C
V
SW
(on) = 10 V
I
SW
-
225
-
mA
+85 C
80
150
-40 C
-
400
425
Dynamic current limit
(t = <0.5
s)
Break switches on, ringing switches off,
apply 1 kV 10/1000
s pulse, with
appropriate protection in place.
-
2.5
-
A
Logic input to switch output isolation
+25 C
V
SW
(T
LINE
, R
LINE
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(T
LINE
, R
LINE
) = 330 V, logic
inputs = gnd
-
0.3
-40 C
V
SW
(T
LINE
, R
LINE
) = 310 V, logic
inputs = gnd
-
0.1
dv/dt sensitivity
-
-
-
200
-
V/
s
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -320 V to gnd
V
SW
(differential) = +260 V to -60 V
I
SW
-
0.1
1
A
+85 C
V
SW
(differential) = -330 V to gnd
V
SW
(differential) = +270 V to -60 V
0.3
-40 C
V
SW
(differential) = -310 V to gnd
V
SW
(differential) = +250 V to -60 V
0.1
R
ON
+25 C
I
SW
(on) = 0 mA, 10 mA
R
ON
-
60
-
+85 C
85
110
-40 C
45
-
DC current limit
+25 C
V
SW
(on) = 10 V
I
SW
-
120
-
mA
+85 C
70
85
-40 C
-
210
Dynamic current limit
(t = <0.5
s)
Break switches off, ringing switches on,
apply 1 kV 10/1000
s pulse, with
appropriate protection in place.
2.5
A
Logic input to switch output isolation
+25 C
V
SW
(T
RING
, T
LINE
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(T
RING
, T
LINE
) = 330 V, logic
inputs = gnd
0.3
-40 C
V
SW
(T
RING
, T
LINE
) = 310 V, logic
inputs = gnd
0.1
dv/dt sensitivity
-
-
-
200
-
V/
s
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
CPC7583
6
www.clare.com
R3.0
1.4.4 Ringing Switch, SW4
1.4.5 TEST
OUT
Switches, SW5 and SW6
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -255 V to +210 V
V
SW
(differential) = +255 V to -210 V
I
SW
-
0.05
1
A
+85 C
V
SW
(differential) = -270 V to +210 V
V
SW
(differential) = +270 V to -210 V
0.1
1
-40 C
V
SW
(differential) = -245 V to +210 V
V
SW
(differential) = +245 V to -210 V
0.05
1
On Voltage
I
SW
(on) = 1 mA
-
1.5
3
V
Ringing generator
current to ground during
ringing
Inputs set for ringing mode
I
RINGING
0.1
0.25
mA
On steady-state current* Inputs set for ringing mode
I
SW
-
150
mA
Surge current*
-
-
-
2
A
Release current
-
I
RINGING
450
-
A
R
ON
I
SW
(on) = 70 mA, 80 mA
R
ON
10
15
Logic input to switch output isolation
+25 C
V
SW
(R
RING
, R
LINE
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(R
RING
, R
LINE
) = 330 V, logic
inputs = gnd
0.3
-40 C
V
SW
(R
RING
, R
LINE
) = 310 V, logic
inputs = gnd
0.1
dv/dt sensitivity
-
-
200
-
V/
s
*Secondary protection and ringing source current limiting must prevent exceeding this parameter.
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -320 V to gnd
V
SW
(differential) = +260 V to -60 V
I
SW
-
0.1
1
A
+85 C
V
SW
(differential) = -330 V to gnd
V
SW
(differential) = +260 V to -60 V
0.3
-40 C
V
SW
(differential) = -310 V to gnd
V
SW
(differential) = +250 V to -60 V
0.1
R
ON
+25 C
I
SW
(on) = 10 mA, 40 mA
R
ON
-
35
-
+85 C
50
70
-40 C
26
-
DC current limit
CPC7583
R3.0
www.clare.com
7
1.4.6 Ringing Test Return Switch, SW7
+25 C
V
SW
(on) = 10 V
I
SW
-
140
-
mA
+85 C
80
100
-
-40 C
-
210
250
Dynamic current limit
(t = <0.5
s)
Break switches in on state, ringing
switches off, apply 1 kV at
10/1000
s pulse, with appropriate
secondary protection in place.
-
2.5
-
A
Logic input to switch output isolation
+25 C
V
SW
(T
TESTout
, T
LINE
, R
TESTout
, R
LINE
)
= 320 V, logic inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(T
TESTout
, T
LINE
, R
TESTout
, R
LINE
)
= 330 V, logic inputs = gnd
I
SW
-
0.3
1
A
-40 C
V
SW
(T
TESTout
, T
LINE
, R
TESTout
, R
LINE
)
= 310 V, logic inputs = gnd
I
SW
-
0.1
1
A
dv/dt sensitivity
-
-
200
-
V/
s
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -320 V to gnd
V
SW
(differential) = +260 to -60 V
I
SW
-
0.1
1
A
+85 C
V
SW
(differential) = -330 V to gnd
V
SW
(differential) = +270 V to -60 V
0.3
-40 C
V
SW
(differential) = -310 V to gnd
V
SW
(differential) = +250 V to -60 V
0.1
R
ON
+25 C
I
SW
(on) = 10 mA, 40 mA
R
ON
-
60
-
+85 C
85
100
-40 C
45
-
DC current limit
+25 C
V
SW
(on) = 10 V
I
SW
70
120
-
mA
+85 C
80
-40 C
210
Logic input to switch output isolation
+25 C
V
SW
(T
RING
, T
TESTin
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(T
RING
, T
TESTin
) = 330 V, logic
inputs = gnd
0.3
-40 C
V
SW
(T
RING
, T
TESTin
) = 310 V, logic
inputs = gnd
0.1
dv/dt sensitivity
-
-
200
-
V/
s
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
CPC7583
8
www.clare.com
R3.0
1.4.7 Ringing Test Switch, SW8
1.4.8 TEST
In
Switches, SW9 and SW10
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -60 V to +175 V
I
SW
-
0.05
1
A
+85 C
0.1
-40 C
0.05
On Voltage
I
SW(ON)
= 1 mA
-
0.75
1.5
V
R
ON
I
SW(ON)
= 70 mA, 80 mA
R
ON
35
-
Release Current
-
-
450
-
A
Logic input to switch output isolation
+25 C
V
SW
(R
RING
, R
TESTin
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(R
RING
, R
TESTin
) = 330 V, logic
inputs = gnd
0.3
-40 C
V
SW
(R
RING
, R
TESTin
) = 310 V, logic
inputs = gnd
0.1
dv/dt sensitivity
-
-
200
-
V/
s
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Off-state leakage current
+25 C
V
SW
(differential) = -320 V to gnd
V
SW
(differential) = -60 V to +260 V
I
SW
-
0.1
1
A
+85 C
V
SW
(differential) = -330 V to gnd
V
SW
(differential) = -60 V to +270 V
0.3
-40 C
V
SW
(differential) = -310 V to gnd
V
SW
(differential) = -60 V to +250 V
0.1
R
ON
+25 C
I
SW
(on) = 10 mA, 40 mA
R
ON
-
35
-
+85 C
50
70
-40 C
26
-
DC current limit
+25 C
V
SW
(on) = 10 V
I
SW
-
160
-
mA
+85 C
80
110
-
-40 C
-
210
250
Logic input to switch output isolation
+25 C
V
SW
(T
TESTin
, R
TESTin
) = 320 V, logic
inputs = gnd
I
SW
-
0.1
1
A
+85 C
V
SW
(T
TESTin
, R
TESTin
) = 330 V, logic
inputs = gnd
0.3
-40 C
V
SW
(T
TESTin
, R
TESTin
) = 310 V, logic
inputs = gnd
0.1
dv/dt sensitivity
-
-
200
-
V/
s
CPC7583
R3.0
www.clare.com
9
1.5 Additional Electrical Characteristics
Parameter
Test Conditions
Symbol
Minimum
Typical
Maximum
Unit
Digital input characteristics
Input low voltage
-
V
IL
-
-
1.5
V
Input high voltage
-
V
IH
3.5
-
-
Input leakage current
(high)
V
DD
= 5.5 V, V
BAT
= -75 V, V
IH
= 5 V
I
IH
-
0.1
1
A
Input leakage current
(low)
V
DD
= 5.5 V, V
BAT
= -75 V, V
IL
= 0 V
I
IL
-
0.1
1
Power requirements
Power consumption in
talk and all-off states
V
DD
= 5 V, V
BAT
= -48 V, measure I
DD
and I
BAT
P
-
4.7
10.5
mW
Power consumption in
all other states
V
DD
= 5 V, V
BAT
= -48 V, measure I
DD
and I
BAT
P
5.2
10.5
V
DD
current in talk and
all-off states
V
DD
= 5 V, V
BAT
= -48 V
I
DD
-
0.9
2.0
mA
V
DD
current in all other
states
I
DD
-
1.0
2.0
V
BAT
current in any state V
DD
= 5V, V
BAT
= -48 V
I
BAT
-
4
10
A
Temperature Shutdown Requirements (temperature shutdown flag is active low)
Shutdown activation
temperature
Not production tested - guarenteed by
design and Quality Control sampling
audits.
T
SD_on
110
125
150
C
Shutdown circuit
hysteresis
T
SD_off
10
-
25
C
CPC7583
10
www.clare.com
R3.0
1.6 Protection Circuitry Electrical Specifications
1.7 Truth Tables
1.7.1 Truth Table for CPC7583xA and CPC7583xB
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Parameters Related to the Diodes in the Diode Bridge
Voltage drop at
continuous current
(50/60 Hz)
Apply dc current limit of break
switches
Forward
Voltage
-
2.8
3.5
V
Voltage drop at surge
current
Apply dynamic current limit of break
switches
Forward
Voltage
-
5
-
Parameters Related to the Protection SCR (when equipped)
Surge current
-
-
-
-
*
A
Trigger current (+25 C)
I
TRIG
60
-
mA
Trigger current (+85 C)
I
TRIG
35
-
Hold current (+25 C)
I
HOLD
110
-
Hold current (+85 C)
I
HOLD
60
70
-
Gate trigger voltage
I
GATE
= I
TRIGGER
V
TBAT
or
V
RBAT
V
BAT
-4
-
V
BAT
-2
V
Reverse leakage current V
BAT
= -48 V
I
VBAT
-
-
1.0
A
On-state voltage
0.5 A, t = 0.5
s
V
TBAT
or
V
RBAT
-3
-
V
2.0 A, t = 0.5
s
-5
-
V
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
V
BAT
must be capable of sourcing I
TRIGGER
for the internal SCR to activate.
State
IN
RINGING
IN
TESTIN
IN
TESTOUT
Latch
T
SD
TEST
IN
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TEST
OUT
Switches
Talk
0
0
0
0
1 or
Floating
1
Off
On
Off
Off
Off
TESTout
0
0
1
Off
Off
Off
Off
On
TESTin
0
1
0
On
Off
Off
Off
Off
Simultaneous
TESTin and
TESTout
0
1
1
On
Off
Off
Off
On
Ringing
1
0
0
Off
Off
Off
On
Off
Ringing
Generator
Test
1
1
0
Off
Off
On
Off
Off
Latched
X
X
X
1
Unchanged Unchanged Unchanged Unchanged Unchanged
All Off
1
0
1
0
Off
Off
Off
Off
Off
1
1
1
0
Off
Off
Off
Off
Off
X
X
X
X
0
2
Off
Off
Off
Off
Off
1
If T
SD
is tied high, thermal shutdown is disabled. If T
SD
is left floating, the thermal shutdown mechanism functions normally.
2
Forcing T
SD
to ground overrides the logic input pins and forces an all off state.
CPC7583
R3.0
www.clare.com
11
1.7.2 Truth Table for CPC7583xC and CPC7583xD
State
IN
RINGING
IN
TESTIN
IN
TESTOUT
Latch
T
SD
TEST
IN
Switches
Break
Switches
Ringing
Test
Switches
Ringing
Switches
TEST
OUT
Switches
Talk
0
0
0
0
1 or
Floating
1
Off
On
Off
Off
Off
TESTout
0
0
1
Off
Off
Off
Off
On
TESTin
0
1
0
On
Off
Off
Off
Off
Simultaneous
TESTin and
TESTout
0
1
1
On
Off
Off
Off
On
Ringing
1
0
0
Off
Off
Off
On
Off
Ringing
Generator
Test
1
1
0
Off
Off
On
Off
Off
Simultaneous
TESTout and
Ringing
Generator
Test
1
1
1
Off
Off
On
Off
On
Latched
X
X
X
1
Unchanged Unchanged Unchanged Unchanged Unchanged
All Off
1
0
1
0
Off
Off
Off
Off
Off
X
X
X
X
0
2
Off
Off
Off
Off
Off
1
If T
SD
is tied high, thermal shutdown is disabled. If T
SD
is left floating, the thermal shutdown mechanism functions normally.
2
Forcing T
SD
to ground overrides the logic input pins and forces an all off state.
CPC7583
12
www.clare.com
R3.0
2. Functional Description
2.1 Introduction
The CPC7583 has the following states:
Talk. Loop break switches SW1, and SW2 closed, all
other switches open.
Ringing. Ringing switches SW3, SW4 closed, all
other switches open.
TESTout. Testout switches SW5, SW6 closed, all
other switches open.
Ringing generator test. SW7, SW8 closed, all
other switches open.
TESTin. Testin switches SW9 and SW10 closed.
Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
Simultaneous test out and ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
All Off. All switches open.
See
"Truth Tables" on page 10
for more information.
The CPC7583 offers break-before-make and
make-before-break switching from the ringing state to
the talk state with simple logic level input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low R
ON
and excellent
matching characteristics. The ringing switch SW4 has
a minimum open contact breakdown voltage of 465 V.
This is sufficiently high, with proper protection, to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
Integrated into the CPC7583 is an over voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC device during a fault condition. Positive and
negative surges are reduced by the current limiting
circuitry and hazardous potentials are diverted to
ground via diodes and the integrated SCR.
Power-cross potentials are also reduced by the current
limiting and thermal shutdown circuits.
To protect the CPC7583 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the T
LINE
and R
LINE
terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
recommended. With proper selection of the secondary
protector, a line card using the CPC7583 will meet all
relevant ITU, LSSGR, TIA/EIA and IEC protection
requirements.
The CPC7583 operates from a +5 V supply only. This
gives the device extremely low idle and active power
consumption and allows use with virtually any range of
battery voltage. The battery voltage is also used by the
CPC7583 as a reference for the integrated protection
circuit. In the event of a loss of battery voltage, the
CPC7583 enters the all-off state.
2.2 Switch Logic
The CPC7583 provides, when switching from the
ringing state to the talk state, the ability to control the
release timing of the ringing switches SW3 and SW4
relative to the state of the loop break switches SW1
and SW2 using simple logic-level input. This is
referred to as a make-before-break or
break-before-make operation. When the line break
switch contacts (SW1 and SW2) are closed (or made)
before the ringing access switch contacts (SW3 and
SW4) are opened (broken), this is referred to
make-before-break operation. Break-before-make
operation occurs when the ringing access contacts
(SW3 and SW4) are opened (broken) before the line
break switch contacts (SW1 and SW2) are closed
(made). With the CPC7583, the make-before-break
and break-before-make operations can easily be
selected by applying the proper sequence of logic
inputs to IN
TESTout
, IN
RINGING
, and IN
TESTin
.
The logic sequences for either mode of operation are
given in
"Make-Before-Break Operation (Ringing to Talk
Transition)" on page 13
and
"Break-Before-Make Operation
(Ringing to Talk Transition)" on page 13
. Logic states and
explanations are given in
"Truth Tables" on page 10
.
Break-before-make operation can also be achieved
using the T
SD
pin as an input. In
"Break-Before-Make
Operation (Ringing to Talk Transition)" on page 13
, lines 2
and 3, it is possible to induce the switches to the all-off
state by grounding T
SD
instead of applying input to the
logic pins. This has the effect of overriding the logic
inputs and forcing the device to the all-off state. For
CPC7583
R3.0
www.clare.com
13
20 Hz ringing hold this input state for 25 ms. During
this hold period, toggle the inputs from the ringing
state to the talk state. After the 25 ms, release T
SD
to
return switch control to the input pins IN
TESTout
,
IN
RINGING
, IN
TESTin
and the latch control pin.
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition)
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition)
2.3 Alternate Break-Before-Make Operation
Note that break-before-make operation can also be
achieved using T
SD
as an input. In lines 2 and 3 of the
table
"Break-Before-Make Operation (Ringing to Talk
Transition)" on page 13
, instead of using the logic input
pins to force the all-off state, force T
SD
to ground. This
overrides the logic inputs and also forces the all off
state. Hold this state for one-half of the ringing cycle.
During this T
SD
forced all-off state, change the inputs
from the power ringing state (IN
RING
= 1, IN
TESTIN
= 0,
IN
TESTOUT
= 0) to the talk state (IN
RING
= 0,
IN
TESTIN
= 0, IN
TESTOUT
= 0). After the hold period,
release T
SD
to return switch control to the input pins
which will set the talk state.
2.4 Data Latch
The CPC7583 has an integrated data latch. The latch
operation is controlled by logic-level input at the
LATCH pin. The data input of the latch are the input
pins, while the output of the data latch is an internal
node used for state control. When the LATCH control
pin is at logic 0, the data latch is transparent and data
control signals flow directly through to state control. A
change in input will be reflected in a change is switch
state. When the LATCH control pin is at logic 1, the
data latch is active and a change in input control will
not affect switch state. The switches will remain in the
position they were in when the LATCH changed from
State
IN
RINGING
IN
TESTIN
IN
TESTOUT
Latch
T
SD
Timing
Break
Switches
1 and 2
Ring
Return
Switch 3
Ring
Access
Switch 4
All Other
Test
Switches
Ringing
1
0
0
0
Floating
-
Off
On
On
Off
Make-bef
ore-break
0
0
0
Floating
SW4 waiting for next
zero-current crossing to turn
off. Maximum time is one-half
of ringing. In this transition
state, current that is limited to
the dc break switch current
limit value will be sourced
from the ring node of the
SLIC.
On
Off
On
Off
Talk
0
0
0
Floating
Zero-cross current has
occurred
On
Off
Off
Off
State
IN
RINGING
IN
TESTIN
IN
TESTOUT
Latch
T
SD
Timing
Break
Switches
1 and 2
Ring
Return
Switch 3
Ring
Access
Switch 4
All Other
Test
Switches
Ringing
1
0
0
0
Floating
-
Off
On
On
Off
All off
1
0
1
Floating
Hold this state for one-half of
ringing cycle. SW4 waiting for
zero current to turn off.
Off
Off
On
Off
All off
1
0
1
Floating
Zero current has occurred.
SW4 has opened
Off
Off
Off
Off
Talk
0
0
0
Floating
Release break switches
On
Off
Off
Off
CPC7583
14
www.clare.com
R3.0
logic 0 to logic 1 and will not respond to changes in
input as long as the latch is at logic 1. The T
SD
input is
not tied to the data latch. Therefore, T
SD
is not
affected by the LATCH input and the T
SD
input will
override state control.
2.5 T
SD
Behavior
Setting T
SD
to +5 V allows switch control using the
logic inputs. This setting, however, also disables the
thermal shutdown circuit and is therefore not
recommended. When using logic controls via the input
pins, T
SD
should be allowed to float. As a result, the
two recommended states when using T
SD
as a control
are 0, which forces the device to an all-off state, or
float, which allows logic inputs to remain active. This
requires the use of an open collector type buffer.
2.6 Ringing Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ringing switch is designed to delay the change in
state until the next zero-crossing. Once on, the switch
requires a zero-current cross to turn off, and therefore
should not be used to switch a pure DC signal. The
switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See Clare application note
AN-144,
Impulse Noise Benefits of Line Card Access Switches
for
more information. The attributes of ringing switch SW4
may make it possible to eliminate the need for a
zero-cross switching scheme. A minimum impedance
of 300
in series with the ringing generator is
recommended.
2.7 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7583. Switch state control is powered
exclusively by the +5 V supply. As a result, the
CPC7583 exhibits extremely low power consumption
during both active and idle states.
The battery voltage is not used for switch control but
rather as a supply for the integrated secondary
protection circuitry. The integrated SCR is designed to
trigger when the voltage at T
BAT
or R
BAT
drops 2 to
4 V below the applied voltage on the V
BAT
pin. This
trigger prevents a fault induced overvoltage event at
the T
BAT
or R
BAT
nodes.
2.8 Battery Voltage Monitor
The CPC7583 also uses the V
BAT
voltage to monitor
battery voltage. If battery voltage is lost, the CPC7583
immediately enters the all-off state. It remains in this
state until the battery voltage is restored. The device
also enters the all-off state if the battery voltage rises
above 10 V and remains in the all-off state until the
battery voltage drops below 15 V. This battery
monitor feature draws a small current from the battery
(less than 1
A typical) and will add slightly to the
device's overall power dissipation.
2.9 Protection
2.9.1 Diode Bridge/SCR
The CPC7583 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
F
GND
. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage source at V
BAT
, the SCR
conducts and faults are shunted to F
GND
via the SCR
or the diode bridge.
In order for the SCR to crowbar or foldback, the on
voltage (see
"Protection Circuitry Electrical
Specifications" on page 10
) of the SCR must be less
negative than the V
BAT
voltage. If the V
BAT
voltage is
less negative than the SCR on state voltage, or if the
V
BAT
supply is unable to source the trigger current, the
SCR will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to a diode
drop above ground and the fault current directed to
ground. The negative cycle of the transient will cause
the SCR to conduct when the voltage exceeds the
battery reference voltage by two to four volts, steering
the current to ground.
2.9.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and restricted by the
dynamic current limit response of the active switches.
During the talk state when a 1000V 10/1000
S pulse
(GR-1089-CORE lightning) is applied to the line
though a properly clamped external protector, the
current into T
LINE
or R
LINE
will be a pulse with a typical
magnitude of 2.5 A and a duration of less than 0.5
s.
CPC7583
R3.0
www.clare.com
15
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
and is limited by the dynamic DC current limit
response of the two break switches. The DC current
limit, specified over temperature, is between 80 mA
and 425 mA, and the circuitry has a negative
temperature coefficient. As a result, if the device is
subjected to extended heating due to power cross
fault, the measured current at T
LINE
or R
LINE
will
decrease as the device temperature increases. If the
device temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
default to the all-off state.
2.10 Temperature Shutdown
The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110 C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, the
voltage out of the T
SD
pin will read 0 V. Normal output
of T
SD
is V
DD
.
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
transient, the device temperature will rise and the
thermal shutdown will activate forcing the switches to
the all-off state. At this point the current measured into
T
LINE
or R
LINE
will drop to zero. Once the device
enters thermal shutdown it will remain in the all-off
state until the temperature of the device drops below
the deactivation level of the thermal shutdown circuit.
This will permit the device to return to normal
operation. If the transient has not passed, current will
flow up to the value allowed by the dynamic DC
current limiting of the switches and heating will begin
again, reactivating the thermal shutdown mechanism.
This cycle of entering and exiting the thermal
shutdown mode will continue as long as the fault
condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector could activate and shunt all current to
ground.
2.11 External Protection Elements
The CPC7583 requires only over-voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional protection on the SLIC side.
The secondary protector must limit voltage transients
to levels that do not exceed the breakdown voltage or
input-output isolation barrier of the CPC7583. A
foldback or crowbar type protector is recommended to
minimize stresses on the CPC7583.
Consult Clare's application note, AN-100, "
Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces
" for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
CPC7583
16
www.clare.com
R3.0
3. Manufacturing Information
3.1 Soldering
3.1.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
of LCAS products using IPC/JEDEC standard
J-STD-020A. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-020A
per the labelled moisture sensitivity level (MSL),
level 1 for the SOIC packages, and level 3 for the MLP
package.
3.1.2 Reflow Profile
The maximum ramp rates, dwell times, and
temperatures of the assembly reflow profile should not
exceed those specified in IPC standard IPC-9502,
table 2. Soldering processes are limited to 220 C
component body temperature.
3.2 Washing
Clare does not recommend ultrasonic cleaning of
LCAS parts.
3.3 Mechanical Dimensions
3.3.1 CPC7583Z - 20 Pin SOIC Package
DIMENSIONS
MM
(INCHES)
0.40 MIN - 1.27 MAX
(0.016 MIN - 0.050 MAX)
0.25 MIN - 0.75 MAX X 45
(0.010 MIN - 0.029 MAX X 45)
0.23 MIN - 0.32 MAX
(0.009 MIN - 0.013 MAX)
0-8
PIN 1
PIN 20
10.00 MIN - 10.65 MAX
MAX)
(0.394 MIN - 0.419
7.40 MIN - 7.60 MAX
MAX)
(0.291 MIN - 0.299
0.10 MIN - 0.30 MAX
(0.004 MIN - 0.012 MAX)
0.33 MIN - 0.51 MAX
(0.013 MIN - 0.020 MAX)
1.27 TYP
(0.050 TYP)
0.508 MAX - 0.762 MAX
MAX)
(0.020 MIN - 0.030
12.60 MIN - 13.00 MAX
MAX)
(0.496 MIN - 0.512
2.35 MIN - 2.65 MAX
(0.093 MIN - 0.104 MAX)
CPC7583
R3.0
www.clare.com
17
3.3.2 CPC7583B - 28 Pin SOIC Package
3.3.3 CPC7583M - 28 Pin MLP Package
NOTE: For optimum solder joint size, MLP package
printed-circuit board pads should extend no more than
.05 mm past the chip post on the short sides, and no
more than .025 mm past the chip posts on the long
sides.
As the metallic pad on the bottom of the MLP package
is connected to the substrate of the die, Clare
recommends that no printed circuit board to traces
cross this area to maintain minimum creepage and
clearance values.
DIMENSIONS
MM
(INCHES)
7.391 MIN/7.595 MAX
(0.291 MIN/0.299 MAX)
10.109 MIN/10.516 MAX
(0.398 MIN/0.414 MAX)
17.983 MIN/18.085 MAX
(0.708 MIN/0.712 MAX)
1.270 TYP
(0.050 TYP)
PIN 28
PIN 1
0.508 MIN/1.016 MAX)
(0.020 MIN/0.040 MAX)
0.2311 MIN/0.3175 MAX
(0.0091 MIN/0.0125MAX)
0.254 MIN/0.737 MAX X 45
(0.010 MIN/0.029 MAX X 45)
2.235 MIN/2.438 MAX
(0.088 MIN/0.096 MAX)
0.366 MIN/0.467 MAX TYP
(0.014 MIN/0.018 MAX TYP)
2.438 MIN/2.642 MAX
(0.096 MIN/0.104 MAX)
0.6600.102
(0.0260.004)
0.37
(0.0146)
Pin 1
TOP VIEW
SIDE VIEW
Seating Plane
Dimensions in mm (inches)
Dimensions and tolerances conform to ANSI Y14.5M-1994
11.0
(0.4334)
7.0
(0.2758)
0.9 0.1
(0.0355 0.0039)
0.02 0.03
(0.0008 0.0012)
0.2
(0.0079)
Bottom side
metallic pad
0.75
(0.0295)
0.33 -0.05 +0.07
(0.0130 -0.0020 +0.0028)
0.55 0.05
(0.0217
0.0020)
0.60
(0.0236)
0.70
(0.0276)
0.18
(0.0071)
0.18
(0.0071)
0.61
(0.0240)
BOTTOM VIEW
5.00.05
(0.19700.0020)
7.5 0.05
(0.2955 0.0020)
3.3.4 CPC7583Z - Tape and Reel Dimensions
3.3.5 CPC7583B - Tape and Reel Dimensions
3.3.6 CPC7583M - Tape and Reel Dimensions
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=3.20 0.15
(0.13 0.01)
+
+
K1=2.60 0.15
(0.10 0.01)
+
+
P=12.00
(0.47)
A0=10.75 0.15
(0.42 0.01)
+
+
B0=13.40 0.15
(0.53 0.01)
+
+
W=24.00 0.3
(0.94 0.01)
+
+
A0=10.75
(0.42)
B0=18.50
(0.73)
W=24.000.03
(0.94.001)
K1=2.60
(0.10)
K0=3.20
(0.13)
P=12.00
(0.47)
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
Top Cover
Tape Thickness
0.102 MAX
(0.004 MAX)
330.2 DIA.
(13.00 DIA)
Embossed Carrier
Embossment
K0=1.35
(0.05)
P=12.00
(0.47)
A0=7.35
(0.29)
B0=11.35
(0.45)
W=24.00 0.3
(0.94 0.01)
+
+
For additional information please visit
www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC7583 - R3.0
Copyright 2003, Clare, Inc.
All rights reserved. Printed in USA.
5/30/2003
PDF 
ZIP