DS-CPC7584-R0.A

www.clare.com

Preliminar

Features

Small 16-pin surface-mount SOIC package and very
small micro-leadframe package (MLP) available

Monolithic IC reliability

Low matched RDS

Eliminates the need for zero cross switching

Flexible switch timing to transition from ringing mode
to idle/talk mode.

Clean, bounce free switching

Tertiary protection consisting of integrated current
limiting, thermal shutdown, and SLIC protection

5 V operation with power consumption less than
10 mW

Intelligent battery monitor

Latched logic level inputs, no drive circuitry

Applications

Central office (CO)

Digital Loop Carrier (DLC)

PBX Systems

Digitally Added Main Line (DAML)

Hybrid Fiber Coax (HFC)

Fiber in the Loop (FITL)

Pair Gain System

Channel Banks

Description

The CPC7584 is a monolithic solid state switch in a
16-pin surface-mount package. It provides the neces-

sary functions to replace two 2-Form-C electro-
mechanical relays on analog line cards found in Cen-
tral Office, Access, and PBX equipment. The device
contains solid state switches for tip and ring line break,
ring injection/ring return and test access. The
CPC7584 requires only a +5V supply and offers
"break-before-make" or "make-before-break" switch
operation using simple logic-level input control.

The CPC7584xC differs from the CPC7584xA/B with
the addition of a logic state. See "Functional Descrip-
tion" on page 10 for more information. The
CPC7584xC also has a higher hold current for the pro-
tection SCR.

Ordering Information

Figure 1. CPC7584 Block Diagram

Part Number

Description

CPC7584BA

SOIC 6-pole LCAS with protection SCR

CPC7584BB

SOIC 6-pole LCAS without protection SCR

CPC7584BC

SOIC 6-pole LCAS with protection SCR and
added logic state

CPC7584MA

MLP 6-pole LCAS with protection SCR

CPC7584MB

MLP 6-pole LCAS without protection SCR

CPC7584MC

MLP 6-pole LCAS with protection SCR and
added logic state

CPC7584xx-TR

Add -TR to the part number when ordering
tape and reel packaging

Ring

TIP

Secondary

Protection

SW1

Break

SW2

Break

SW3

Ringing

Return

SW5

Test-In

SW6

Test-In

SW4

Ringing

Access

SCR

and Trip

Circuit

SLIC

Ring Generator

BAT

Reference

(16)

CPC7584

Battery

LINE

(2)

BAT

(15)

BAT

(14)

(3)

(12)

Test-In

(13)

RING

(5)

TEST-IN

(4)

RING

CPC7584

Line Card Access Switch

CPC7584

www.clare.com

R0.A

Preliminar

1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.3 Ring Return Switch, SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.4 Ringing Access Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.5 Test-In Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 CPC7584xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 CPC7584xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5 Washing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CPC7584

Rev. 0.A

www.clare.com

Preliminar

1. Specifications

1.1 Absolute Maximum Ratings (at 25° C)

1.2 Electrical Characteristics, T

= -40° C to +85° C

Unless otherwise specified, minimum and maximum
values are production testing requirements. Typical
values are characteristic of the device and are the
result of engineering evaluations. Typical values are
provided for information purposes only and are not
part of the testing requirements.

Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an
extended period may degrade the device and affect its reli-
ability.

1.2.1 Power Supply Specifications

1.2.2 Break Switches, SW1 and SW2

Parameter

Minimum Maximum

Unit

Operating temperature

-40

+110

°C

Storage temperature

-40

+150

°C

Operating relative humidity

Pin soldering temperature
(10 seconds max)

+260

°C

+5 V power supply

Battery Supply

-85

Logic input voltage

Logic input to switch output
isolation

330

Switch isolation (SW1,
SW2, SW3, SW5, SW6)

330

Switch Isolation (SW4)

480

Supply

Minimum Typical Maximum

Unit

+4.5

+5.0

+5.5

BAT

-19

-72

BAT

is used only as a reference for internal protection circuitry. If V

BAT

rises above

-10 V, the device will enter the all-off state and will remain in the all-off state until the
battery drops below -15 V.

ESD Rating (Human Body Model)

1000 V

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

+25° C

(differential) = -320 V to GND

(differential) = -60 V to +260 V

0.1

+85° C

(differential) = -330 V to GND

(differential) = -60 V to +270 V

0.3

-40° C

(differential) = -310 V to GND

(differential) = -60 V to +250 V

0.1

RDS

+25° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

14.5

+85° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

20.5

-40° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

10.5

RDS

match

Per on-resistance test condition of
SW1, SW2R

SW1-R

SW2

Magnitude

0.15

0.8

DC current limit

+25° C

(on) = ±10 V

300

+85° C

(on) = ±10 V

160

-40° C

(on) = ±10 V

400

425

CPC7584

www.clare.com

Rev. 0.A

Preliminar

1.2.3 Ring Return Switch, SW3

Dynamic current limit
(t = <0.5

Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.

2.5

Logic input to switch output isolation

+25° C

LINE

, R

LINE

) = ±320 V, logic

inputs = gnd

0.1

+85° C

LINE

, R

LINE

) = ±330 V, logic

inputs = gnd

0.3

-40° C

LINE

, R

LINE

) = ±310 V, logic

inputs = gnd

0.1

dv/dt sensitivity

Applied voltage = 100 V p-p square
wave at 100 Hz

200

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

+25° C

(differential) = -320 V to GND

(differential) = -60 V to +260 V

0.1

+85° C

(differential) = -330 V to GND

(differential) = -60 V to +270 V

0.3

-40° C

(differential) = -310 V to GND

(differential) = -60 V to +250 V

0.1

RDS

+25° C

(on) = ±0 mA, ±10 mA

+85° C

(on) = ±0 mA, ±10 mA

100

-40° C

(on) = ±0 mA, ±10 mA

DC current limit

+25° C

(on) = ±10 V

135

+85° C

(on) = ±10 V

-40° C

(on) = ±10 V

210

Dynamic current limit
(t = <0.5

Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.

2.5

Logic input to switch output isolation

+25° C

RING

, T

LINE

) = ±320 V, logic

inputs = gnd

0.1

+85° C

RING

, T

LINE

) = ±330 V, logic

inputs = gnd

0.3

-40° C

RING

, T

LINE

) = ±310 V, logic

inputs = gnd

0.1

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

CPC7584

Rev. 0.A

www.clare.com

Preliminar

1.2.4 Ringing Access Switch, SW4

1.2.5 Test-In Switches, SW5 and SW6

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

+25° C

(differential) = -255 V to +210 V

(differential) = +255 V to -210 V

0.05

+85° C

(differential) = -270 V to +210 V

(differential) = +270 V to -210 V

0.1

-40° C

(differential) = -245 V to +210 V

(differential) = +245 V to -210 V

0.05

On Voltage

(on) = ± 1 mA

1.5

Ring generator current
during ring

= 5 V, INaccess = 0

0.1

0.25

Surge current

Release current

300

RDS

(on) = ±70 mA, ±80 mA

8.5

Logic input to switch output isolation

+25° C

RING

, R

LINE

) = ±320 V, logic

inputs = gnd

0.05

+85° C

RING

, R

LINE

) = ±330 V, logic

inputs = gnd

0.1

-40° C

RING

, R

LINE

) = ±310 V, logic

inputs = gnd

0.05

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Off-state leakage current

+25° C

(differential) = -320 V to GND

(differential) = -60 V to +260 V

0.1

+85° C

(differential) = -330 V to GND

(differential) = -60 V to +270 V

0.3

-40° C

(differential) = -310 V to GND

(differential) = -60 V to +250 V

0.1

RDS

+25° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

+85° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

-40° C

LINE

= ±10 mA, ±40 mA, T

BAT

= -2 V

DC current limit

+25° C

(on) = ±10 V

175

+85° C

(on) = ±10 V

110

-40° C

(on) = ±10 V

210

250

Dynamic current limit
(t = <0.5

Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.

2.5

CPC7584

www.clare.com

Rev. 0.A

Preliminar

1.3 Additional Electrical Characteristics

Logic input to switch output isolation

+25° C

ACCESS

, T

LINE

) = ±320 V, logic

inputs = gnd

0.1

+85° C

ACCESS

, T

LINE

) = ±330 V, logic

inputs = gnd

0.3

-40° C

ACCESS

, T

LINE

) = ±310 V, logic

inputs = gnd

0.1

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Parameter

Conditions

Symbol

Minimum

Typical

Maximum

Unit

Digital input characteristics

Input low voltage

1.5

Input high voltage

3.5

Input leakage current
(high)

= 5.5 V, V

BAT

= -75 V, V

log

= 5 V

log

0.1

Input leakage current
(low)

= 5.5 V, V

BAT

= -75 V, V

log

= 0 V

log

0.1

Power requirements

Power dissipation in
idle/talk and all-off
states

= 5 V, V

BAT

= -48 V

, I

BAT

5.5

Power dissipation in
ringing and access
states

(on) = ±10 V

6.5

current in idle/talk

and all off states

= 5 V

1.1

2.0

current in ringing

and access states

1.3

2.0

BAT

current in idle/talk

and all off states

BAT

= -48 V

BAT

0.1

BAT

current in ringing

and access states

BAT

0.1

Temperature Shutdown Requirements (temperature shutdown flag is active low)

Shutdown activation
temperature

110

125

150

°C

Shutdown circuit hyster-
esis

°C

CPC7584

Rev. 0.A

www.clare.com

Preliminar

1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition)

1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition)

1.4 Alternate Break-Before-Make Operation

Break-before-make operation can also be achieved
using TSD as an input. In lines 2 and 3 of "Break-
Before-Make Operation (Ringing to Idle/Talk Transi-
tion)" on page 6, instead of using the logic input pins to
force the all-off state, force TSD to ground. This over-
rides the logic inputs and also forces the all off state.
Hold this state for 25 ms. During this 25 ms all-off
state, toggle the inputs from the ringing state (Ring =
5 V, Test-In = 0 V) to the idle/talk state
(Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to
return switch control to the input pins which will set the
idle talk state.

When using the CPC7584 in this mode, forcing TSD
to ground overrides the input pins and force an all off
state. Setting TSD to +5 V allows switch control via the
logic input pins. However, setting TSD to +5 V also
disables the thermal shutdown mechanism. This is not
recommended. Therefore, to allow switch control via
the logic input pins, allow TSD to float.

When using TSD as an input, the two recommended
states are 0 (overrides logic input pins and forces all
off state) and float (allows switch control via logic input
pins and the thermal shutdown mechanism is active).
This may require use of an open-collector buffer.

Test-In

Input

TSD

State

Timing

Break

Switches

1 and 2

Ring

Return

Switch 3

Ring

Access

Switch 4

Line

Access

Switches

5 and 6

0 V

5 V

Floating

Ringing

Open

Closed

Open

0 V

Floating

Make-

before-

break

SW4 waiting for next zero-current crossing
to turn off. Maximum time is one-half of ring-
ing. In this transition state, current that is
limited to the dc break switch current limit
value will be sourced from the ring node of
the SLIC.

Closed

Open

Closed

Open

0 V

Floating

Idle/Talk

Zero-cross current has occurred

Closed

Open

Test-In

Input

TSD

State

Timing

Break

Switches

1 and 2

Ring

Return

Switch 3

Ring

Access

Switch 4

Line

Access

Switches

5 and 6

0 V

5 V

Floating

Ringing

Open

Closed

Open

5 V

Floating

All-off

Hold this state for at least 25 ms. SW4 wait-
ing for zero current to turn off.

Open

Closed

Open

5 V

Floating

SW4 has opened.

Open

0 V

Floating

Idle/Talk

Release Break Switches

Closed

Open

CPC7584

www.clare.com

Rev. 0.A

Preliminar

1.5 Protection Circuitry Electrical Specifications

1.6 CPC7584xA/B Truth Table

1.7 CPC7584xC Truth Table

Parameter

Conditions

Symbol

Minimum

Typical

Maximum Unit

Parameters Related to the Diodes in the Diode Bridge

Voltage drop at continu-
ous current (50/60 Hz)

Apply ± dc current limit of break
switches

Forward

Voltage

2.1

Voltage drop at surge
current

Apply ± dynamic current limit of break
switches

Forward

Voltage

Parameters Related to the Protection SCR

Surge current

Trigger current (+25° C) -

TRIG

Hold current (+25° C)

HOLD

100

Trigger current (+85° C) -

TRIG

Hold current (+85° C)

HOLD

Gate trigger voltage

Trigger current

BAT

-4

BAT

-2

Reverse leakage cur-
rent

BAT

1.0

On-state voltage

0.5 A, t = 0.5 ms

-3

2.0 A, t = 0.5 ms

-5

*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.

State

Ring

Test-In

TSD

Tip

Break

Switch

Ring

Break

Switch

Ringing

Return
Switch

Ring

Switch

Tip Test-In

Switch

Ring Test-

In Switch

Idle/Talk

0 V

5 V/Floating

Off

Power Ring-
ing

5 V

0 V

Off

Test-In

0 V

5 V

Off

All Off

5 V

Off

All off

Don't care

0 V

Off

If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.

State

Ring

Test-In

TSD

Tip

Break

Switch

Ring

Break

Switch

Ringing

Return
Switch

Ring

Switch

Tip Test-In

Switch

Ring Test-

In Switch

Idle/Talk

0 V

5 V/Floating

Off

Power Ring-
ing

5 V

0 V

Off

Test Monitor

0 V

5 V

Off

All Off

5 V

Off

All off

Don't care

0 V

Off

If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.

CPC7584

www.clare.com

Rev. 0.A

Preliminar

3. Functional Description

3.1 Introduction

The CPC7584xA/B has four states:

Idle/Talk. Line break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test-in switches SW5 and SW6 open.

Ringing. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test-in
switches SW5 and SW6 open.

Test-In. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 open, and test-in
switches SW5 and SW6 closed.

All off. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 open, and loop test
switches SW5 and SW6 open.

In the CPC7584xC, the test-in state is replaced with
the test monitor state, defined as: line break switches
SW1 and SW2 closed, Ringing switches SW3 and
SW4 open, and test-in switches SW5 and SW6
closed.

The CPC7584 offers break-before-make and make-
before-break switching with simple logic-level input
control. Solid-state switch construction means no
impulse noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via
logic-level input so no additional driver circuitry is
required. The line break switches SW1 and SW2 are
linear switches that have exceptionally low RDS

and excellent matching characteristics. The ringing
access switch SW4 has a breakdown voltage rating of
greater than 480 V. This is sufficiently high, with
proper protection, to prevent breakdown in the pres-
ence of a transient fault condition (i.e., passing the
transient on to the ring generator).

Integrated into the CPC7584 is a diode bridge/SCR
clamping circuit, current limiting, and a thermal shut-
down mechanism to provide protection to the SLIC
device during a fault condition. Positive and negative
surges are reduced by the current limiting circuitry and
steered to ground via diodes and the integrated SCR.
Power-cross transients are also reduced by the cur-
rent limiting and thermal shutdown circuits. Note that
only the CPC7584xA and CPC7584xC parts include
the integrated protection SCR.

To protect the CPC7584 from an overvoltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the maxi-

mum breakdown voltage of the switches. To minimize
the stress on the solid-state contacts, use of a fold-
back or crowbar type secondary protector is recom-
mended. With proper selection of the secondary
protector, a line card using the CPC7582BC will meet
all relevant ITU, LSSGR, FCC and UL protection
requirements.

The CPC7584 operates from a +5 V supply only. This
gives the device extremely low idle and active power
dissipation and allows use with virtually any range of
battery voltage. A battery voltage is also used by the
CPC7584 as a reference for the integrated protection
circuit. In the event of a loss of battery voltage, the
CPC7584 enters the all-off state.

3.2 Switch Timing

The CPC7584 provides, when switching from the ring-
ing state to the idle/talk state, the ability to control the
release timing of the ringing access switches SW3
and SW4 relative to the state of the line break
switches SW1 and SW2 using simple logic-level input.
This is referred to a make-before-break or break-
before-make operation. When the line break switch
contacts (SW1 and SW2) are closed (or made) before
the ringing access switch contacts (SW3 and SW4)
are opened (or broken), this is referred to make-
before-break operation. Break-before-make operation
occurs when the ringing access contacts (SW3 and
SW4) are opened (broken) before the line break
switch contacts (SW1 and SW2) are closed (made).
With the CPC7584, the make-before-break and break-
before-make operations can easily be selected by
applying logic-level inputs to pins 9 and 10 (IN

RING

and IN

TEST-IN

) of the device.

The logic sequences for either mode of operation are
given in "Make-Before-Break Operation (Ringing to
Idle/Talk Transition)" on page 6 and "Break-Before-
Make Operation (Ringing to Idle/Talk Transition)" on
page 6. Logic states and explanations are given in
"CPC7584xA/B Truth Table" on page 7.

Break-before-make operation can also be achieved
using pin 7 (TSD) as an input. In "Break-Before-Make
Operation (Ringing to Idle/Talk Transition)" on page 6
lines 2 and 3, it is possible to induce the switches to
the all-off state by grounding pin 7 (TSD) instead of
apply logic input to the pins. This has the effect of
overriding the logic inputs and forcing the device to the
all-off state. Hold this input state for 25 ms. During this
hold period, toggle the inputs from the ringing state

CPC7584

Rev. 0.A

www.clare.com

Preliminar

(10) to the idle/talk state (00). After the 25 ms, release
pin 7 (TSD) to return the switch control to the input
pins 9 and 10 and reset the device to the idle/talk
state.

Setting TSD to +5 V allows switch control using the
logic pins 9 and 10. This setting, however, also dis-
ables the thermal shutdown circuit and is therefore not
recommended. When using logic controls via the input
pins 9 and 10, pin 7 (TSD) should be allowed to float.
As a result, the two recommended states when using
pin 7 (TSD) as a control are 0, which forces the device
to the all-off state, or float, which allows logic inputs to
pins 9 and 10 to remain active. This may require the
use of an open-collector buffer.

3.3 Ring Access Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off,
the ring access switch is designed to delay the change
in state until the next zero-crossing. Once on, the
switch requires a zero-current cross to turn off, and
therefore should not be used to switch a pure DC sig-
nal. The switch will remain in the on state no matter
what logic input until the next zero crossing. For
proper operation, pin 12 (R

RING

) should be connected

using proper impedance to a ring generator or other
AC source. These switching characteristics will reduce
and possibly eliminate overall system impulse noise
normally associated with ringing access switches. The
attributes of ringing access switch SW4 may make it
possible to eliminate the need for a zero-cross switch-
ing scheme. A minimum impedance of 300

in series

with the ring generator is recommended.

3.4 Power Supplies

Both a +5 V supply and battery voltage are connected
to the CPC7584. CPC7584 switch state control is
powered exclusively by the +5 V supply. As a result,
the CPC7584 exhibits extremely low power dissipation
during both active and idle states.

The battery voltage is not used for switch control but
rather as a reference for the integrated secondary pro-
tection circuitry. The integrated SCR is designed to
trigger when pin 3 (T

BAT

) or pin 14 (R

BAT

) drops 2 to

4 V below the battery. This trigger prevents a fault
induced overvoltage event at the T

BAT

or R

BAT

nodes.

3.5 Battery Voltage Monitor

The CPC7584 also uses the voltage reference to
monitor battery voltage. If battery voltage is lost, the
CPC7582BC immediately enters the all-off state. It
remains in this state until the battery voltage is

restored. The device also enters the all-off state if the
battery voltage rises above 10 V and remains in the
all-off state until the battery voltage drops below
15 V. This battery monitor feature draws a small cur-
rent from the battery (less than 1 mA typical) and will
add slightly to the device's overall power dissipation.

3.6 Protection

3.6.1 Diode Bridge/SCR

The CPC7584 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is con-
ducted through the diode bridge to ground. Voltage is
clamped to the diode drop above ground. During a
negative transient of 2 to 4 V more negative than the
battery, the SCR conducts and faults are shunted to
ground via the SCR and diode bridge.

In order for the SCR to crowbar or foldback, the on
voltage (see "Protection Circuitry Electrical Specifica-
tions" on page 7) of the SCR must be less negative
than the battery reference voltage. If the battery volt-
age is less negative the SCR on voltage, the SCR will
not crowbar, however it will conduct fault currents to
ground.

For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to the
diode drop above ground and the fault current directed
to ground. The negative cycle of the transient will
cause the SCR to conduct when the voltage exceeds
the battery reference voltage by two to four volts,
steering the current to ground.

3.6.2 Current Limiting function

If a lightning strike transient occurs when the device in
the talk/idle state, the current is passed along the line
to the integrated protection circuitry and limited by the
dynamic current limit response of break switches SW1
and SW2. When a 1000V 10/1000 pulse (LSSGR
lightning) is applied to the line though a properly
clamped external protector, the current seen at pins 2
(T

BAT

) and pin 15 (R

BAT

) will be a pulse with a typical

magnitude of 2.5 A and a duration of less than 0.5 ms.

If a power-cross fault occurs with the device in the talk/
idle state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
and is limited by the dynamic DC current limit
response of the two break switches. The DC current
limit, specified over temperature, is between 80 mA

CPC7584

www.clare.com

Rev. 0.A

Preliminar

and 425 mA, and the circuitry has a negative tempera-
ture coefficient. As a result, if the device is subjected
to extended heating due to power cross fault, the mea-
sured current at pin 2 (T

BAT

) and pin 15 (R

BAT

) will

decrease as the device temperature increases. If the
device temperature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
default to the all-off state.

3.7 Temperature Shutdown

The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 7
(TSD) will read 0 V. Normal output of TSD is +V

If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will typi-
cally not activate. But in an extended power-cross
transient, the device temperature will rise and the ther-
mal shutdown will activate forcing the switches to the
all-off state. At this point the current measured at pin 3
(T

BAT

) and pin 14 (R

BAT

) will drop to zero. Once the

device enters thermal shutdown it will remain in the
all-off state until the temperature of the device drops
below the activation level of the thermal shutdown cir-
cuit. This will return the device to the state prior to
thermal shutdown. If the transient has not passed, cur-
rent will flow at the value allowed by the dynamic DC
current limiting of the switches and heating will begin
again, reactivating the thermal shutdown mechanism.
This cycle of entering and exiting the thermal shut-
down mode will continue as long as the fault condition
persists. If the magnitude of the fault condition is great
enough, the external secondary protector could acti-
vate and shunt all current to ground.

The thermal shutdown mechanism of the CPC7584
can be disable by applying +V

to pin 7 (TSD).

3.8 External Protection Elements

The CPC7584 requires only one overvoltage second-
ary protector on the loop side of the device. The inte-
grated protection feature described above negates the
need for protection on the line side. The secondary
protector limits voltage transients to levels that do not
exceed the breakdown voltage or input-output isola-
tion barrier of the CPC7584. A foldback or crowbar
type protector is recommended to minimize stresses
on the device.

Consult Clare's application note, AN-100, "

Designing

Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces

" for equations related

to the specifications of external secondary protectors,
fused resistors and PTCs.

3.9 Data Latch

The CPC7584 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10 (IN

RING

)

and pin 9 (IN

TEST-IN

) of the device while the output of

the data latch is an internal node used for state con-
trol. When LATCH control pin is at logic 0, the data
latch is transparent and data control signals flow
directly through to state control. A change in input will
be reflected in a change is switch state. When LATCH
control pin is at logic 1, the data latch is active and a
change in input control will not affect switch state. The
switches will remain in the position they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. The TSD input is not tied to the data latch.
Therefore, TSD is not affected by the LATCH input
and the TSD input will override state control via pin 10
(IN

RING

) and pin 9 (IN

TEST-IN

) and the LATCH.

Preliminar

lead to moisture induced delamination and cracking of
the component. To prevent this, this component must
be handled in accordance with IPC/JEDEC standard
J-STD-020A per the labeled moisture sensitivity level
(MSL), level 1 for the SOIC package, and level 2 for
the MLP package.

4.4.2 Reflow Profile

The maximum ramp rates, dwell times, and tempera-
tures of the assembly reflow profile should not exceed
those specified in IPC/JEDEC standard J-STD-020A,
which were used to determine the moisture sensitivity
level of this component.

4.5 Washing

Clare does not recommend ultrasonic cleaning of
LCAS parts.

For additional information please visit

www.clare.com

Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CPC7584xC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CPC7584xC