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Copyright 1994-1999 Cologne Chip Designs GmbH
All Rights Reserved
The information presented can not be considered as
assured characteristics. Data can change without notice.
Parts of the information presented may be protected by
patent or other rights.
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Revision History
Date
Remarks
Feb. 1999
Changes made on: CLKDEL register bit description.
Jan. 1999
New chip released: HFC-S PCI A is compliant to PCI Spec 2.2. The old chip
HFC-S PCI is not recommended for new projects.
Sep. 1998
Changes made on: Electrical characteristics, Part List: C3 and C4 must be 22pF.
Aug. 1998
Changes made on: FIFO_EN register bit description.
Aug. 1998
Changes made on: Part List: C3 and C4 must be 47pF, C5 and C6 have been
removed.
July 1998
changes made on: PCI buffer signaling and power supply environment, PCI
configuration registers, B_MODE register bit description
July 1998
changes made on: Block diagram, sample circuitry, Part List: Q2 and Q3 must be
BC850C instead of BC848B
June 1998
schematic of PCI sample board corrected; digital part added
May 1998
changes made on: RESET characteristics, PCI modes supported, PCI buffer
signaling environment, PCI configuration registers, timer, FIFO counters location in
MW, automatically D-channel frame repetition, FIFO initialisation, TRxR register
bit description, CTMT register bit description, CHIP_ID register bit description,
FIFO_EN register bit description, TRM register bit description, electrical
characteristics, S/T module part numbers and manufacturers, sample circuitry
Eintrachtstrasse 113
D-50668 Kln
Germany
Tel.: +49 (0) 221 / 912 96 04
Fax: +49 (0) 221 / 912 96 05
http://www.CologneChip.com
http://www.CologneChip.de
CologneChip@t-online.de
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Contents
1 General description.................................................................................................................................. 6
1.1 Applications ............................................................................................................................................ 7
2 Pin description.......................................................................................................................................... 8
2.1 PCI bus interface..................................................................................................................................... 8
2.2 Auxiliary port........................................................................................................................................ 10
2.3 S/T interface transmit signals ............................................................................................................... 10
2.4 S/T interface receive signals ................................................................................................................. 10
2.5 Oscillator............................................................................................................................................... 11
2.6 GCI/IOM2 bus interface ....................................................................................................................... 11
2.7 GCI/IOM2 Timeslot enable signals ...................................................................................................... 11
2.8 EEPROM interface ............................................................................................................................... 11
2.9 Power supply......................................................................................................................................... 12
2.10 RESET characteristics ........................................................................................................................ 12
3 Functional description........................................................................................................................... 13
3.1 PCI-interface ......................................................................................................................................... 13
3.1.1 PCI access types used by HFC-S PCI............................................................................................ 13
3.1.2 PCI modes supported..................................................................................................................... 13
3.1.3 PCI buffer signaling and power supply environment .................................................................... 13
3.1.4 PCI configuration registers............................................................................................................ 14
3.2 Internal HFC-S PCI register description............................................................................................... 17
3.2.1 Registers of the S/T section........................................................................................................... 18
3.2.2 Registers of the GCI/IOM2 bus section ........................................................................................ 19
3.2.3 Interrupt and status registers.......................................................................................................... 20
3.3 Timer..................................................................................................................................................... 21
3.4 FIFOs .................................................................................................................................................... 22
3.4.1 FIFO counters location in Memory Window ................................................................................ 23
3.4.2 FIFO data location in Memory Window ....................................................................................... 24
3.4.3 FIFO channel operation ................................................................................................................. 25
3.4.3.1 Send channels (B1, B2 and D transmit) ................................................................................. 25
3.4.3.2 Automatically D-channel frame repetition............................................................................. 26
3.4.3.3 FIFO full condition in send channels ..................................................................................... 26
3.4.3.4 Receive Channels (B1, B2 and D receive)............................................................................. 26
3.4.3.5 FIFO full condition in receive channels................................................................................. 28
3.4.3.6 FIFO initialisation .................................................................................................................. 28
3.4.4 Transparent mode of HFC-S PCI .................................................................................................. 29
4 Register bit description ......................................................................................................................... 30
4.1 Register bit description of S/T section ................................................................................................. 30
4.2 Register bit description of GCI/IOM2 bus section ............................................................................... 33
4.3 Register bit description of CONNECT register.................................................................................... 36
4.4 Register bit description of auxiliary and cross data registers ............................................................... 37
5 Electrical characteristics ....................................................................................................................... 42
6 Timing characteristics ........................................................................................................................... 46
6.1 PCI bus timing ...................................................................................................................................... 46
6.2 GCI/IOM2 bus clock and data alignment for Mitel ST
TM
bus.............................................................. 46
6.3 GCI/IOM2 timing.................................................................................................................................. 47
6.4 EEPROM access ................................................................................................................................... 48
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7 S/T interface circuitry ........................................................................................................................... 49
7.1 External receiver circuitry .................................................................................................................... 49
7.2 External transmitter circuitry................................................................................................................ 50
7.3 Oscillator circuitry ................................................................................................................................ 53
7.4 EEPROM circuitry................................................................................................................................ 53
7.5 PME pin circuitry.................................................................................................................................. 54
8 State matrices for NT and TE............................................................................................................... 55
8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT ......................................... 55
8.2 Activation/deactivation layer 1 for finite state matrix for TE .............................................................. 56
9 Binary organisation of the frames........................................................................................................ 57
9.1 S/T frame structure ............................................................................................................................... 57
9.2 GCI frame structure .............................................................................................................................. 58
10 Clock synchronisation ......................................................................................................................... 59
10.1 Clock synchronisation in NT-mode .................................................................................................... 59
10.2 Clock synchronisation in TE-mode .................................................................................................... 60
11 HFC-S PCI package dimensions ........................................................................................................ 61
12 ISDN PCI card sample circuitry with HFC-S PCI........................................................................... 62
Figures
Figure 1: HFC-S PCI block diagram............................................................................................................. 7
Figure 2: Pin Connection .............................................................................................................................. 8
Figure 3: HFC-S PCI in I/O address mapped mode.................................................................................... 17
Figure 4: HFC-S PCI in memory address mapped mode............................................................................ 17
Figure 5: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 25
Figure 6: FIFO Data Organisation .............................................................................................................. 27
Figure 7: Function of the CONNECT register bits..................................................................................... 36
Figure 8: GCI/IOM2 bus clock and data alignment.................................................................................... 46
Figure 9: External receiver circuitry........................................................................................................... 49
Figure 10: External transmitter circuitry .................................................................................................... 50
Figure 11: Oscillator Circuitry.................................................................................................................... 53
Figure 12: EEPROM circuitry .................................................................................................................... 53
Figure 13: PME pin circuitry ...................................................................................................................... 54
Figure 14: Frame structure at reference point S and T ............................................................................... 57
Figure 15: Single channel GCI format........................................................................................................ 58
Figure 16: Clock synchronisation in NT-mode .......................................................................................... 59
Figure 17: Clock synchronisation in TE-mode ........................................................................................... 60
Figure 18: HFC-S PCI package dimensions ............................................................................................... 61
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Tables
Table 1: PCI command types ...................................................................................................................... 13
Table 2: PCI configuration registers' initial values..................................................................................... 17
Table 3: S/T module part numbers and manufacturer ................................................................................ 52
Table 4: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 55
Table 5: Activation/deactivation layer 1 for finite state matrix for TE ...................................................... 56
Timing Diagrams
Timing diagram 3: GCI/IOM2 timing......................................................................................................... 47
Timing diagram 4: EEPROM access .......................................................................................................... 48
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