Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 1 of 14
http://www.cypress.com
PRELIMINARY
C9851
Product Features
Six pairs of current referenced differential clocks
Two 3V 180
displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
Cypress Spread Spectrum for EMI reduction
48 Pin SSOP Package
Product Description
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations. It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the
Cypress B9852. The 2 Mref clock outputs are 180
degrees out of phase and are used for interfacing with
the Direct Rambus Clock Generator (DRCG), C9820,
C9821, or C9822. This device integrates the Cypress
spread spectrum technology for optimum EMI
reduction.
Frequency Selection Table
SEL 100/133
SELA
SELB
CPU(1:6), CPU#(1:6)
3VMref,
3Vmref_b
3V66
REF
0
0
0
100 MHz
50 MHz
66.67 MHz
14.318 MHz
0
0
1
100 MHz
Low
Low
Low
0
1
0
200 MHz
50 MHz
66.67 MHz
14.318 MHz
0
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
0
133.3 MHz
66.67 MHz
66.67 MHz
14.318 MHz
1
0
1
25 MHz
50 MHz
66.67 MHz
14.318 MHz
1
1
0
200 MHz
66.7 MHz
66.67 MHz
14.318 MHz
1
1
1
REF/2
REF/4
REF
REF
Block Diagram
Table 1
Pin Configuration
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDDA
VSSA
SelA
SelB
Spread#
PwrDwn#
VDD
VSS
VDDC
CPU1
CPU1#
VSSC
CPU2
CPU2#
VDDC
CPU3
CPU3#
VSSC
CPU4
CPU4#
VDDC
CPU5
CPU5#
VSSC
CPU6
CPU6#
VDDC
I_Ref
VSSA
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OSC
VCO
I
Control
VDDA
I_Ref
VSSI
VDDR
VSSR
REF
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
Spread#
SelA
SelB
SEL100/133
XOUT
XIN
MultSel(0:1)
PwrDwn#
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 2 of 14
http://www.cypress.com
PRELIMINARY
C9851
Pin Description
PIN No.
Pin Name
I/O
Description
8
3VMref
O
Output clock for driving the DRCG device. See table 1, page1 for frequency selection.
9
3VMref_b
O
Output clock for driving the DRCG device. See table 1, page1 for frequency selection. It
is 180 degrees out of phase (inverted) from the 3VMref clock.
23
Spread#
PU
When asserted low, this pin invokes Spread Spectrum functionality. Spread spectrum is
applicable to CPU(1:6), CPU(1:6)#, 3VMref, 3VMref_b, and 3V66 clocks. This pin has a
250K
internal Pull-up.
45,42,39,36,
33,30
CPU(1:6)
44,41,38,35,
32,29
CPU(1:6)#
O
Differential host clock outputs. These outputs are used in pairs, (CPU1-1#, CPU2-2#,
CPU3-3#, CPU4-4#, CPU5-5#, and CPU6-6#) for differential clocking of the host bus.
CPU(1:6)# are 180 degrees out of phase with their complements, CPU(1:6). See table 1,
page 1 for frequency selection.
27
I_Ref
P
This pin establishes the reference current for the internal current steering buffers of the
CPU clocks. A resistor is connected from this pin to ground to set the value of this current.
See applications data on page 9 of this data sheet for details.
14
3V66
O
Fixed 66.67 MHz clock output for driving the IMI B9852 buffer device.
24
PwrDwn#
PU
When asserted low, this pin Invokes power-down mode by shutting off all the clocks,
disabling all internal circuitry, and shutting down the crystal oscillator. The 3VMref,
3VMref_B, 3V66, REF and CPU clocks are driven low during this condition. It has a
250K
internal Pull-up.
22, 21
SelA, SelB
PD
Input select pins. See table 1, page 1. Each pin has a 250K
internal Pull-down
16
SEL100/133
PU
Input select pin. See table 1, page 1. It has a 250K
internal Pull-up
5
XOUT
O
Crystal Buffer output pin. Connects to a crystal only. When an external signal other than
a crystal is used or when in Test mode, this pin is kept unconnected.
4
XIN
I
Crystal Buffer input pin. Connects to a crystal, or an external single ended input clock
signal.
2
REF
O
A buffered output clock of the signal applied at Xin. Typically, 14.31818MHz.
18, 17
MultSel (0,1)
I
These input select pins configure the LOH current (and thus the VOH swing amplitude) of
the CPU clock output pairs. Each pin has a 250K
internal Pull-up. See the table 5 for
current and resistor values.
3
VDDR
P
3.3V power supply pins for Ref clock and crystal buffer.
46,40,34,28
VDDC
P
3.3V power supply pins for CPU(1:6) / CPU(1:6)# outputs.
11, 48
VDD
P
3.3V power supply pins for common supply to the core.
13
VDDL
P
3.3V power supply pins for 3V66 output.
19, 25
VDDA
P
3.3V power supply pins for internal current reference circuitry and internal PLL.
7
VDDM
P
3.3V power supply pin for 3Vmref and 3Vmref_b outputs
1, 6
VSSR
P
Ground pins for the Ref clock and crystal buffer.
31, 37, 43
VSSC
P
Ground pins for the CPU(1:6)/CPU(1:6)# outputs.
12, 47
VSS
P
Ground pins for common supply to the core.
15
VSSL
P
Ground pin for the 3V66 output.
20, 26
VSSA
P
Ground pin for internal current reference circuitry and internal PLL.
10
VSSM
P
Ground pin for 3Vmref and 3Vmref_b outputs.
Note: Definition of I/O column pneumonic on pin description table above:
I = Input pin, O = output pin, P = power supply pin, PU = This indicated that a bi-directional pin contains a device internal pull-up
resistor. This will insure that this pin of the device will be seen by the internal logic as a logic 1 level. Likewise pins with a PD
designation are guaranteed to be seen as a logic 0 level if no external level setting circuitry is present at power up.
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 3 of 14
http://www.cypress.com
PRELIMINARY
C9851
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.5V
Maximum Input Voltage Relative to VSS: VDD + 0.7V
Storage Temperature:
-65C to + 150C
Operating Temperature:
0C to +70C
Maximum ESD protection
2000V
Maximum Power Supply:
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
(VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V
5%, TA = 0
C to +70
C)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL1
-
-
0.8
Vdc
Input High Voltage
VIH1
2.0
-
-
Vdc
Note 1
Input Low Current (@Vin =
VSS)
IIL
-16
-4
A
Input High Current (@Vin =
VDD)
IIH
0
5
A
For internal Pull up resistors, Note 1
and Note 2
-
Input Low Current (@Vin =
VSS)
IIL
0
-
A
Input High Current (@Vin =
VDD)
IIH
4
16
A
For internal Pull down resistors, Note
1 and Note 2
Tri-State leakage Current
Ioz
-
-
10
A
Static Supply Current
Idd
-
-
30
mA
PwrDwn=Low
Dynamic Supply Current
Isdd
-
-
200
mA
133 MHz CPU, Note 3
Input pin capacitance
Cin
-
-
5
pF
Output pin capacitance
Cout
-
-
6
pF
Pin Inductance
Lpin
-
-
7
nH
Crystal pin capacitance
Cxtal
34
36
38
pF
Measured from Pin to Ground. See
crystal specification section presented
later in this data sheet.
Crystal Startup time
Txs
-
-
40
S
From Stable 3.3V power supply.
Internal Pull-up and Pull-
down resistor value
Rpi
200
250
500
K
Note1:
Applicable to input signals: Sel100/133, Sel(A:B)), Spread#, PWRDN#, MultSel(0:1)
Note2:
Although internal pull-up or Pull-Down resistors have a typical value of 250K, this value may vary between 200K and 500K.
Note3:
All outputs loaded as per the maximum capacitive table in this data sheet.
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 4 of 14
http://www.cypress.com
PRELIMINARY
C9851
AC Parameters
(VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V
5%, TA = 0
C to +70
C)
133 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
TPeriod
CPU[(1:6), (1:6)#] period -
7.35
7.65
9.85
10.2
nS
1, 2
Tr / Tf
CPU[(1:6), (1:6)#] rise and fall times
175
450
175
450
pS
2, 3
TSKEW1
skew from any CPU pair to any CPU pair
-
150
-
150
pS
2, 4, 5
TSKEW2
skew from package to package
-
100
-
100
pS
2, 4, 5
TCCJ
CPU[(1:6), (1:6)#] Cycle to Cycle Jitter
-
150
-
150
pS
2, 4, 5
Vover
CPU[(1:6), (1:6)#] Overshoot
Voh+0.2
Voh+0.2
V
2,10
Vunder
CPU[(1:6), (1:6)#] Undershoot
-0.2
-0.2
V
2, 10
Vcrossover
CPU(1:6) to CPU(1:6)# crossover point
45%Voh
55%Voh
45%Voh
55%Voh
V
2, 4
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
3V(MREF, MREF_B) period
15.0
15.3
20.0
20.4
nS
4, 5
THIGH
3V(MREF, MREF_B) high time
5.25
-
7.5
-
nS
2, 6
TLOW
3V(MREF, MREF_B) low time
5.05
-
7.3
-
nS
2, 7
Tr / Tf
3V(MREF, MREF_B) rise and fall times
0.4
1.6
0.4
1.6
nS
2, 3
TSKEW
3VMREF to 3VMREF_B skew
-
250
-
250
pS
2, 4, 5, 11
TCCJ
3V(MREF, MREF_B) Cycle to Cycle Jitter
-
250
-
250
pS
2, 4, 5
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
3V66 period
15.0
16.0
15.0
15.2
nS
1, 2, 4
THIGH
3V66 high time
5.25
-
5.25
-
nS
2,6
TLOW
3V66 low time
5.05
-
5.05
-
nS
2, 7
Tr / Tf
3V66 rise and fall times
0.5
2.0
0.5
2.0
nS
2, 3
TCCJ
3V66 Cycle to Cycle Jitter
-
300
-
300
pS
2, 4, 5
Tduty
Duty Cycle
45
55
45
55
%
2, 4
TPeriod
REF period
69.8413
71.0
69.8413
71.0
nS
1, 2, 4
Tr / Tf
REF rise and fall times
1.0
4.0
1.0
4.0
nS
2, 3
TCCJ
REFCycle to Cycle Jitter
-
1000
-
1000
pS
2, 4
Tduty
Duty Cycle
45
55
45
55
%
2, 4
tpZL, tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
9
tpLZ, tpZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
nS
9
tstable
All clock Stabilization from power-up
3
3
mS
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) continued
Note 1: This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1uS duration, with a crystal
center frequency of 14.31818MHz
Note 2: All outputs loaded as per table 2 below.
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for
CPU[(1:6), (1:6)#] signals. (see Figs.7A & 7B)
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figs.7A
& 7B).
Note 5: This measurement is applicable with Spread ON or Spread OFF.
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4V (see Figs. 7A & 7B)
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V. (see Figs. 7A & 7B)
Note 9: As this function is available through SEL(A,B), therefore, the time specified is guaranteed by design.
Note 10: Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
Note 11: 3VMref and 3VMref_b are 180 degrees out of phase, therefore, the skew is measured between the rising edge of one and the falling edge
of the other.
Clock Generator for Pentium
III Server and Workstation Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07068 Rev. **
05/04/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 5 of 14
http://www.cypress.com
PRELIMINARY
C9851
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) (Continued)
Output name
Max Load
CPU[(1:6), (1:6)#]
Rs = 33.2
, Rp = 49.9
3VMref, 3VMref_b
30 pF
REF
20 pF
3V66
30 pF
Table 2.
Lumped Test Load Configurations
The following shows lumped test load configurations for the differential Host Clock Outputs.
(MULTsel1 = 0, MULTsel0 = 1)
Fig.1A
Test Nodes
Rp
Rs
Rs
49.9ohm
49.9ohm
Rp
33.2ohm
33.2ohm
PDF 
ZIP