Three-PLL General Purpose
FLASH Programmable Clock Generator
CY22392
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07013 Rev. *D
Revised June 22, 2004
1CY2295
Features
Three integrated phase-locked loops
Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)
Improved Linear Crystal Load capacitors
Flash programmability
Field programmable
Low-jitter, high-accuracy outputs
Power-management options (Shutdown, OE, Suspend)
Configurable Crystal drive strength
Frequency Select via 3 external LVTTL Inputs
3.3V operation
16-pin TSSOP packages
CyClocksRTTM Support
Benefits
Generates up to 3 unique frequencies on 6 outputs up
to 200 MHz from an external source. Functional
upgrade for current CY2292 family.
Allows for 0 ppm Frequency Generation and Frequency
Conversion under the most demanding applications.
Improves frequency accuracy over temperature, age,
process, and initial offset.
Non-Volatile programming enables easy customi-
zation, ultra-fast turnaround, performance tweaking,
design timing margin testing, inventory control, lower
part count, and more secure product supply. In
addition, any part in the family can also be programmed
multiple times which reduces programming errors and
provides an easy upgrade path for existing designs.
In-house programming of samples and prototype
quantities is available using the CY3672 FTG Devel-
opment Kit. Production quantities are available through
Cypress Semiconductor's value added Distribution
partners or by using third party programmers from BP
Microsystems, HiLo Systems, and others.
Performance suitable for high-end multimedia, commu-
nications, industrial, A/D Converters, and consumer
applications.
Supports numerous low-power application schemes
and reduces EMI by allowing unused outputs to be
turned off.
Adjust Crystal Drive Strength for compatibility with
virtually all crystals.
3-Bit External Frequency Select Options for PLL1,
CLKA, and CLKB.
Industry-standard supply voltage.
Industry-standard packaging saves on board space.
Easy to use software support for design entry.
XTALIN
XTALOUT
S2/SUSPEND
S1
S0
SHUTDOWN/OE
CONFIGURATION
FLASH
OSC.
XBUF
PLL1
CLKE
11 BIT P
8 BIT Q
PLL2
11 BIT P
8 BIT Q
PLL3
11 BIT P
8 BIT Q
4x4
Switch
Crosspoint
Divider
7 BIT
Divider
7 BIT
Divider
7 BIT
Divider
7 BIT
Divider
/2,3, or 4
CLKA
CLKB
CLKC
CLKD
Logic Block Diagram
CY22392
Document #: 38-07013 Rev. *D
Page 2 of 8
Pin Configuration
1
2
3
4
5
6
7
8
9
10
CLKC
V
DD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
SHUTDOWN/OE
S2/SUSPEND
AV
DD
S1
S0
GND
CLKA
CLKB
16-pin TSSOP
11
12
13
14
15
16
CY22392
Selector Guide
Part Number Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY22392FC
6
8 MHz30 MHz (external crystal)
1 MHz166 MHz (reference clock)
Up to 200 MHz
Commercial Temperature
CY22392FI
6
8 MHz30 MHz (external crystal)
1 MHz150 MHz (reference clock)
Up to 166 MHz
Industrial Temperature
Pin Description
Name
Pin Number
Description
CLKC
1
Configurable clock output C
V
DD
2
Power supply
AGND
3
Analog Ground
XTALIN
4
Reference crystal input or external reference clock input
XTALOUT
5
Reference crystal feedback
XBUF
6
Buffered reference clock output
CLKD
7
Configurable clock output D
CLKE
8
Configurable clock output E
CLKB
9
Configurable clock output B
CLKA
10
Configurable clock output A
GND
11
Ground
S0
12
General Purpose Input for Frequency Control; bit 0
S1
13
General Purpose Input for Frequency Control; bit 1
AV
DD
14
Analog Power Supply
S2/
SUSPEND
15
General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control
input.
SHUTDOWN/OE
16
Places outputs in three-state condition and shuts down chip when LOW. Optionally,
only places outputs in tristate condition and does not shut down chip when LOW
CY22392
Document #: 38-07013 Rev. *D
Page 3 of 8
Operation
The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility,
improved performance, and incorporates many features that
reduce PLL sensitivity to external system issues.
The device has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to the crosspoint switch. The output of PLL1 is also sent to a
/2, /3, or /4 synchronous post-divider that is output through
CLKE. The frequency of PLL1 can be changed by external
CMOS inputs, S0, S1, S2. See the following section on
General-Purpose Inputs for more details.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the crosspoint switch.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross-point switch.
General-Purpose Inputs
S0, S1, and S2 are general-purpose inputs that can be
programmed to allow for eight different frequency settings.
Options that may be switched with these general purpose
inputs are as follows; the frequency of PLL1, the output divider
of CLKB, and the output divider of CLKA.
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
For example: the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibility. The following is a description of each output.
CLKA's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
S2 controls which of the two programmable registers is loaded
into CLKA's 7-bit post divider. See the section
"General-Purpose Inputs" for more information.
CLKB's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. Each of the eight possible combinations of S0, S1,
and S2 controls which of the two programmable registers is
loaded into CLKA's 7-bit post divider. See the section
"General-Purpose" Inputs for more information.
CLKC's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKE's output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
XBUF is simply the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the V
DD
pins will be less than 5
A (typical). After leaving shutdown
mode, the PLLs will have to relock.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combi-
nation. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
CY22392
Document #: 38-07013 Rev. *D
Page 4 of 8
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKACLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple V
DD
pins, there are no power supply
sequencing requirements. The part will not be fully operational
until all V
DD
pins have been brought up to the voltages
specified in the "Operating Conditions" table.
All grounds should be connected to the same ground plane.
CyClocksRTTM Software
CyClocksRT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
you to see the power consumption of your specific configu-
ration. You can download a copy of CyClocksRT for free on
Cypress's web site at www.cypress.com.
Junction Temperature Limitations
It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package
JA
is
115 C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ...............................................0.5V to +7.0V
DC Input Voltage ............................0.5V to + (AV
DD
+ 0.5V)
Storage Temperature ................................. 65
C to +125C
Junction Temperature...................................................125
C
Data Retention @ Tj = 125
C.................................>10 years
Maximum Programming Cycles .......................................100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................................
2000V
Latch up (per JEDEC 17) .................................... > 200 mA
Operating Conditions
[1]
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
/AV
DD
Supply Voltage
3.135
3.3
3.465
V
T
A
Commercial Operating Temperature, Ambient
0
+70
C
Industrial Operating Temperature, Ambient
40
+85
C
C
LOAD_OUT
Max. Load Capacitance
15
pF
f
REF
External Reference Crystal
8
30
MHz
External Reference Clock
[2]
, Commercial
1
166
MHz
External Reference Clock
[2]
, Industrial
1
150
MHz
t
PU
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
500
ms
Notes:
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
CY22392
Document #: 38-07013 Rev. *D
Page 5 of 8
Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
I
OH
Output High Current
[3]
V
OH
= V
DD
0.5, V
DD
= 3.3 V
12
24
mA
I
OL
Output Low Current
[3]
V
OL
= 0.5V, V
DD
= 3.3 V
12
24
mA
C
XTAL_MIN
Crystal Load Capacitance
[3]
Capload at minimum setting
6
pF
C
XTAL_MAX
Crystal Load Capacitance
[3]
Capload at maximum setting
30
pF
C
LOAD_IN
Input Pin Capacitance
[3]
Except crystal pins
7
pF
V
IH
HIGH-Level Input Voltage
CMOS levels,% of AV
DD
70%
AV
DD
V
IL
LOW-Level Input Voltage
CMOS levels,% of AV
DD
30%
AV
DD
I
IH
Input HIGH Current
V
IN
= AV
DD
0.3 V
<1
10
A
I
IL
Input LOW Current
V
IN
= +0.3 V
<1
10
A
I
OZ
Output Leakage Current
Three-state outputs
10
A
I
DD
Total Power Supply Current
3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz
100
mA
3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz
50
mA
I
DDS
Total Power Supply Current in
Shutdown Mode
Shutdown active
5
20
A
Switching Characteristics
Parameter
Name
Description
Min.
Typ.
Max.
Unit
1/t
1
Output Frequency
[3, 4]
Clock output limit, Commercial
200
MHz
Clock output limit, Industrial
166
MHz
t
2
Output Duty Cycle
[3, 5]
Duty cycle for outputs, defined as t
2
t
1
,
Fout < 100 MHz, divider >= 2, measured at V
DD
/2
45%
50%
55%
Duty cycle for outputs, defined as t
2
t
1
,
Fout > 100 MHz or divider = 1, measured at V
DD
/2
40%
50%
60%
t
3
Rising Edge Slew Rate
[3]
Output clock rise time, 20% to 80% of V
DD
0.75
1.4
V/ns
t
4
Falling Edge Slew
Rate
[3]
Output clock fall time, 20% to 80% of V
DD
0.75
1.4
V/ns
t
5
Output three-state
Timing
[3]
Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
150
300
ns
t
6
Clock Jitter
[3, 6]
Peak-to-peak period jitter, CLK outputs measured
at V
DD
/2
400
ps
t
7
Lock Time
[3]
PLL Lock Time from Power-up
1.0
3
ms
Notes:
3. Guaranteed by design, not 100% tested.
4. Guaranteed to meet 20%80% output thresholds and duty cycle specifications.
5. Reference Output duty cycle depends on XTALIN duty cycle.
6. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
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