Three-PLL General Purpose

FLASH Programmable Clock Generator

CY22392

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07013 Rev. *C

Revised December 14, 2002

Features

Benefits

Three integrated phase-locked loops

Generates up to 3 unique frequencies on 6 outputs up to
200 MHz from an external source. Functional upgrade for cur-
rent CY2292 family.

Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit
Post Divide)

Allows for 0 ppm Frequency Generation and Frequency Conver-
sion under the most demanding applications.

Improved Linear Crystal Load Capacitors

Improves frequency accuracy over temperature, age, process,
and initial offset.

Flash programmability

Non-Volatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing mar-
gin testing, inventory control, lower part count, and more secure
product supply. In addition, any part in the family can also be
programmed multiple times which reduces programming errors
and provides an easy upgrade path for existing designs.

Field programmable

In-house programming of samples and prototype quantities is
available using the CY3672 FTG Development Kit. Production
quantities are available through Cypress Semiconductor's value
added Distribution partners or by using third party programmers
from BP Microsystems, HiLo Systems, and others.

Low-jitter, high-accuracy outputs

Performance suitable for high-end multimedia, communications,
industrial, A/D Converters, and consumer applications.

Power-management options (Shutdown, OE, Suspend)

Supports numerous low-power application schemes and reduc-
es EMI by allowing unused outputs to be turned off.

Configurable Crystal Drive Strength

Adjust Crystal Drive Strength for compatibility with virtually all
crystals.

Frequency Select via 3 External LVTTL Inputs

3-Bit External Frequency Select Options for PLL1, CLKA, and
CLKB.

3.3V operation

Industry-standard supply voltage.

16-pin TSSOP Packages

Industry-standard packaging saves on board space.

CyClocksRTTM Support

Easy to use software support for design entry.

CYClocks RT is a trademark of Cypress Semiconductor Corporation

XTALIN

XTALOUT

S2/SUSPEND

SHUTDOWN/OE

CONFIGURATION

FLASH

OSC.

XBUF

PLL1

CLKE

11 BIT P

8 BIT Q

PLL2

11 BIT P

8 BIT Q

PLL3

11 BIT P

8 BIT Q

4x4

Switch

Crosspoint

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

Divider

7 BIT

Divider
/2,3, or 4

CLKA

CLKB

CLKC

CLKD

Logic Block Diagram

CY22392

Document #: 38-07013 Rev. *C

Page 2 of 9

Pin Configuration

CLKC

AGND

XTALIN

XTALOUT

XBUF

CLKD

CLKE

SHUTDOWN/OE

S2/SUSPEND

GND

CLKA

CLKB

16-pin TSSOP

CY22392

Selector Guide

Part Number

Outputs

Input Frequency Range

Output Frequency Range

Specifics

CY22392FC

8 MHz30 MHz (external crystal)
1 MHz166 MHz (reference clock)

Up to 200 MHz

Commercial Temperature

CY22392FI

8 MHz30 MHz (external crystal)
1 MHz150 MHz (reference clock)

Up to 166 MHz

Industrial Temperature

Pin Summary

Name

Pin Number

Description

CLKC

Configurable clock output C

Power supply

AGND

Analog Ground

XTALIN

Reference crystal input or external reference clock input

XTALOUT

Reference crystal feedback

XBUF

Buffered reference clock output

CLKD

Configurable clock output D

CLKE

Configurable clock output E

CLKB

Configurable clock output B

CLKA

Configurable clock output A

GND

Ground

General Purpose Input for Frequency Control; bit 0

General Purpose Input for Frequency Control; bit 1

Analog Power Supply

S2/
SUSPEND

General Purpose Input for Frequency Control; bit 2. Optionally Suspend mode control
input.

SHUTDOWN/OE

Places outputs in three-state condition and shuts down chip when LOW. Optionally,
only places outputs in tristate condition and does not shut down chip when LOW

CY22392

Document #: 38-07013 Rev. *C

Page 3 of 9

Operation

The CY22392 is an upgrade to the existing CY2292. The new
device has a wider frequency range, greater flexibility, im-
proved performance, and incorporates many features that re-
duce PLL sensitivity to external system issues.

The device has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be out-
put on up to six pins. These three PLLs are completely pro-
grammable.

Configurable PLLs

PLL1 generates a frequency that is equal to the reference di-
vided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
crosspoint switch. The output of PLL1 is also sent to a /2, /3,
or /4 synchronous post-divider that is output through CLKE.
The frequency of PLL1 can be changed by external CMOS
inputs, S0, S1, S2. See the following section on General-Pur-
pose Inputs for more details.

PLL2 generates a frequency that is equal to the reference di-
vided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
crosspoint switch.

PLL3 generates a frequency that is equal to the reference di-
vided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross-point switch.

General-Purpose Inputs

S0, S1, and S2 are general-purpose inputs that can be pro-
grammed to allow for eight different frequency settings. Op-
tions that may be switched with these general purpose inputs
are as follows; the frequency of PLL1, the output divider of
CLKB, and the output divider of CLKA.

CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.

For example: the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.

Crystal Input

The input crystal oscillator is an important feature of this device
because of its flexibility and performance features.

The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, processes, performances, and qualities.

The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate ca-
pacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, Communications, or
other applications that are sensitive to absolute frequency re-
quirements.

The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.

For driven clock inputs the input load capacitors may be com-
pletely bypassed. This enables the clock chip to accept driven
frequency inputs up to 166 MHz. If the application requires a
driven input, then XTALOUT must be left floating.

Output Configuration

Under normal operation there are four internal frequency
sources that may be routed via a programmable crosspoint
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. In
addition, many outputs have a unique capability for even
greater flexibility. The following is a description of each output.

CLKA's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post di-
vider derives its value from one of two programmable regis-
ters. Each of the eight possible combinations of S0, S1, S2
controls which of the two programmable registers is loaded
into CLKA's 7-bit post divider. See the section "General-Pur-
pose Inputs" for more information.

CLKB's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post di-
vider derives its value from one of two programmable regis-
ters. Each of the eight possible combinations of S0, S1, and
S2 controls which of the two programmable registers is loaded
into CLKA's 7-bit post divider. See the section "General-Pur-
pose" Inputs for more information.

CLKC's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post di-
vider derives its value from one programmable register.

CLKD's output originates from the crosspoint switch and goes
through a programmable 7-bit post divider. The 7-bit post di-
vider derives its value from one programmable register.

CLKE's output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.

XBUF is simply the buffered reference.

The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While driv-
ing multiple loads is possible with the proper termination it is
generally not recommended.

Power Saving Features

The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, the reference oscillator, and
all other active components. The resulting current on the V

pins will be less than 5

A (typical). After leaving shutdown

mode, the PLLs will have to relock.

The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combina-
tion. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.

CY22392

Document #: 38-07013 Rev. *C

Page 4 of 9

Improving Jitter

Jitter Optimization Control is useful in mitigating problems re-
lated to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the out-
puts (CLKACLKD). This prevents the output edges from
aligning, allowing superior jitter performance.

Power Supply Sequencing

For parts with multiple V

pins, there are no power supply

sequencing requirements. The part will not be fully operational
until all V

pins have been brought up to the voltages speci-

fied in the "Operating Conditions" table.

All grounds should be connected to the same ground plane.

CyClocks RTTM Software

CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocks RT also has a power estimation feature that allows
you to see the power consumption of your specific configura-
tion. You can download a copy of CyClocks RT for free on
Cypress's web site at www.cypress.com.

Junction Temperature Limitations

It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package

115 C/W. Use the CyClocks RT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum rat-
ings.

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ...............................................0.5V to +7.0V

DC Input Voltage ............................0.5V to + (AV

+ 0.5V)

Storage Temperature ................................. 65

C to +125

Junction Temperature ...................................................125

Data Retention @ Tj = 125

C.................................>10 years

Maximum Programming Cycles .......................................100

Package Power Dissipation...................................... 350 mW

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ..........................................
2000V

Latch up (per JEDEC 17) .................................... > ±200 mA

Operating Conditions

[1]

Parameter

Description

Min.

Typ.

Max.

Unit

/AV

Supply Voltage

3.135

3.3

3.465

Commercial Operating Temperature, Ambient

+70

Industrial Operating Temperature, Ambient

+85

LOAD_OUT

Max. Load Capacitance

REF

External Reference Crystal

MHz

External Reference Clock

[2]

, Commercial

166

MHz

External Reference Clock

[2]

, Industrial

150

MHz

Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)

0.05

500

Notes:

Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.

External input reference clock must have a duty cycle between 40% and 60%, measured at V

/2.

CY22392

Document #: 38-07013 Rev. *C

Page 5 of 9

Electrical Characteristics

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit

Output High Current

[3]

= V

0.5, V

= 3.3 V

Output Low Current

[3]

= 0.5V, V

= 3.3 V

XTAL_MIN

Crystal Load Capacitance

[3]

Capload at minimum setting

XTAL_MAX

Crystal Load Capacitance

[3]

Capload at maximum setting

LOAD_IN

Input Pin Capacitance

[3]

Except crystal pins

HIGH-Level Input Voltage

CMOS levels,% of AV

70%

LOW-Level Input Voltage

CMOS levels,% of AV

30%

Input HIGH Current

= AV

0.3 V

Input LOW Current

= +0.3 V

Output Leakage Current

Three-state outputs

Total Power Supply Current

3.3V Power Supply; 2 outputs @
166 MHz; 4 outputs @ 83 MHz

100

3.3V Power Supply; 2 outputs @
20 MHz; 4 outputs @ 40 MHz

DDS

Total Power Supply Current
in Shutdown Mode

Shutdown active

Switching Characteristics

Parameter

Name

Description

Min.

Typ.

Max.

Unit

1/t

Output Frequency

[3, 4]

Clock output limit, Commercial

200

MHz

Clock output limit, Industrial

166

MHz

Output Duty Cycle

[3, 5]

Duty cycle for outputs, defined as t

Fout < 100 MHz, divider >= 2, measured at
V

45%

50%

55%

Duty cycle for outputs, defined as t

Fout > 100 MHz or divider = 1, measured at
V

40%

50%

60%

Rising Edge Slew
Rate

[3]

Output clock rise time, 20% to 80% of V

0.75

1.4

V/ns

Falling Edge Slew
Rate

[3]

Output clock fall time, 20% to 80% of V

0.75

1.4

V/ns

Output three-state Tim-
ing

[3]

Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches

150

300

Clock Jitter

[3, 6]

Peak-to-peak period jitter, CLK outputs mea-
sured at V

400

Lock Time

[3]

PLL Lock Time from Power-up

1.0

Notes:

Guaranteed by design, not 100% tested.

Guaranteed to meet 20%80% output thresholds and duty cycle specifications.

Reference Output duty cycle depends on XTALIN duty cycle.

Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.

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