Pentium

Processor Compatible

Clock Synthesizer/Driver

CY2254A

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07203 Rev. *A

Revised December 14, 2002

Features

· Multiple clock outputs to meet requirements of most

Pentium

motherboards

-- Four pin-selectable CPU clocks @ 66.66 MHz, 60.0

MHz, and 50.0 MHz for support of Intel Triton

PCIset

based PC

-- 55.0 MHz pin-selectable CPU clock also available (

option only)

-- Six PCI clocks at 1/2 CPU Clock frequency

-- One I/O clock @ 24 MHz

-- One Keyboard Controller clock @ 12 MHz (

1 option)

or one Universal Serial Bus clock @ 48 MHz
(

2 option)

-- Two Ref. clocks @ 14.318 MHz

-- Ref. 14.318 MHz Xtal oscillator input

· CPU clock jitter < 200 ps cycle-to-cycle
· Low skew outputs

-- < 250 ps between CPU clocks

-- < 250 ps between PCI clocks

-- < 500 ps between CPU and PCI clocks (

2 option)

-- CPU clock leads PCI clock by +1 ns min. to +4 ns

max. (

1 option)

· Freq. stability = 0.01% (max.)
· Output duty cycle 45% min. to 55% max.
· Test mode support (

1 option only)

· 3.3V or 5.0V operation
· Internal pull-up resistors on S0, S1, and OE inputs

Functional Description

The CY2254A is a Clock Synthesizer/Driver that provides the
multiple clocks required for a Pentium-based PC. The
CY2254A has low-skew outputs (< 250 ps between the CPU
Clocks, < 250 ps between the PCI Clocks). In addition, the
CY2254A CPU clock outputs have less than 200 ps cy-
cle-to-cycle jitter. Finally, both the PCI and CPU clock outputs
meet the 1 V/ns slew rate requirement of a Pentium proces-
sor-based system.

The CY2254A accepts a 14.318 MHz reference signal as its
input. The CY2254A has 2 PLLs, one of which generates the
CPU and PCI clocks, and the other generates the I/O and Key-
board Controller or USB clocks. The CY2254A runs off either
a 3.3V or 5V supply.

The CY2254A is available in two options. The

1 option sup-

ports the Intel Triton PCIset and provides a 12 MHz keyboard
clock on pin 25. The

2 option provides a 48 MHz USB clock

on pin 25 and supports the Cyrix

M1 processor.

Intel and Pentium are registered trademarks of Intel Corporation.
Triton is a trademark of Intel Corporation.
Cyrix is a registered trademark of Cyrix Corporation.

Pin Configuration

Logic Block Diagram

XTALOUT

XTALIN

REF0 (14.318 MHz)

14.318

MHz

OSC.

11
12

Top View

XTALIN

XTALOUT

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

REF0

REF1

SEEBELOW

IOCLK

PCICLK2

PCICLK3

PCICLK4

PCICLK5
V

PCICLK1

PCICLK0

REF1 (14.318 MHz)

IOCLK (24 MHz)

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

PCICLK0

SYS

PLL

CPU

PLL

ROM

DELAY

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

SOIC

USBCLK (48 MHz)

KBDCLK (12 MHz)

OPTION

PIN 25

KBDCLK

12 MHz

USBCLK

48 MHz

1 option only

CY2254A

Document #: 38-07203 Rev. *A

Page 2 of 8

Pin Summary

Name

Description

Voltage supply

XTALIN

[1]

Reference crystal input

XTALOUT

[1]

Reference crystal feedback

Ground

Output Enable, Active HIGH (internal pull-up resistor to V

)

CPUCLK0

CPU clock output

CPUCLK1

CPU clock output

Voltage supply

CPUCLK2

CPU clock output

CPUCLK3

CPU clock output

Ground

CPU clock select input, bit 1 (internal pull-up resistor to V

)

CPU clock select input, bit 0 (internal pull-up resistor to V

)

Voltage supply

PCICLK0

PCI clock output

PCICLK1

PCI clock output

Ground

PCICLK5

PCI clock output

PCICLK4

PCI clock output

Voltage supply

PCICLK3

PCI clock output

PCICLK2

PCI clock output

Ground

IOCLK

I/O clock output (24 MHz)

KBDCLK

Keyboard controller clock output (12 MHz)

USBCLK

Universal Serial Bus clock output (48 MHz)

Voltage supply

REF1

Reference clock output (14.318 MHz)

REF0

Reference clock output (14.318 MHz)

Function Table

Option

XTALIN

CPUCLK

PCICLK

Ref. Clock

Output

IOCLK

KBDCLK

1 only

USBCLK

2 only

14.318 MHz High-Z

High-Z

14.318 MHz 50.0 MHz

25.0 MHz

14.318 MHz 24 MHz

12 MHz

48 MHz

14.318 MHz 60.0 MHz

30.0 MHz

14.318 MHz 24 MHz

12 MHz

48 MHz

14.318 MHz 66.66 MHz

33.33 MHz

14.318 MHz 24 MHz

12 MHz

48 MHz

TCLK

[2]

TCLK/2

TCLK/4

TCLK

TCLK/4

TCLK/8

14.318 MHz 55.0 MHz

27.5 MHz

14.318 MHz 24 MHz

48 MHz

Notes:

For best accuracy, use a parallel-resonant crystal, C

LOAD

= 17 pF.

TCLK is a test clock on XTALIN (pin 2) during test mode.

CY2254A

Document #: 38-07203 Rev. *A

Page 3 of 8

PCI Clock Driver Strength Requirements

· Matched impedances on both rising and falling edges on

the output drivers

· Output impedance: 25

(typical) measured at 1.5V

· Maximum output impedance: 40

measured at 1.5V

CPU Clock Driver Strength Requirements

· Matched impedances on both rising and falling edges on

the output drivers

· Output impedance: 25

(typical) measured at 1.5V

· Maximum output impedance: 40

measured at 1.5V

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage

........................................................-

0.5 to +7.0V

Input Voltage

................................................. -

0.5V to V

+ 0.5

Storage Temperature (Non-Condensing)

.... -

C to +150

Junction Temperature ............................................... +150

Package Power Dissipation.............................................. 1W

Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015)

Operating Conditions

[3]

Parameter

Description

Min.

Max.

Unit

Supply Voltage 3.3V
Supply Voltage 5.0V

3.135

4.5

3.6
5.5

V
V

Operating Ambient Temperature

Max. Capacitive Load on

CPUCLK
PCICLK
IOCLK
KBDCLK / USBCLK
REF0
REF1

20
30
20
20
30
15

(REF)

Reference Frequency, Oscillator Nominal Value

14.318

MHz

Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)

0.05

Electrical Characteristics

= 3.135V

3.6V, or 5.0V

10%, T

= 0

C to +70

Parameter

Description

Test Conditions

Min.

Max.

Unit

High-level Input Voltage

Except Crystal Inputs

2.0

Low-level Input Voltage

Except Crystal Inputs

0.8

[4]

High-level Output Voltage

= V

Min.

= 6 mA

CPUCLK

2.4

= 12 mA

PCICLK, REF0

= 4 mA

KBDCLK, USBCLK

= 8 mA

REF1

[4]

Low-level Output Voltage

= V

Min.

= 6 mA

CPUCLK

0.4

= 12 mA

PCICLK, REF0

= 4 mA

KBDCLK, USBCLK

= 8 mA

REF1

Input High Current

= V

DD,

= 3.3V

= V

DD,

= 5.0V

Input Low Current

= 0 V, V

= 3.3V

100

= 0 V, V

= 5.0V

250

Output Leakage Current

Three-state

+10

Power Supply Current

= 3.6V, V

= 0 or V

= 5.5V, V

= 0 or V

150

mA
mA

CY2254A

Document #: 38-07203 Rev. *A

Page 4 of 8

Notes:

Electrical parameters are guaranteed with these operating conditions.

Guaranteed by design, not tested.

Electrical Characteristics

= 3.135V

3.6V, or 5.0V

10%, T

= 0

C to +70

C (continued)

Parameter

Description

Test Conditions

Min.

Max.

Unit

Switching Characteristics

[5]

Parameter

Output

Name

Description

Min.

Max.

Unit

All

Output Duty Cycle

[6]

= t

45%

55%

[4]

CPUCLK, PCICLK

Output Rising and Fall-
ing Edge Rate

Measured between 0.4 and 2.4V

V/ns

[4]

REF, KBDCLK, USBCLK

Rise Time

Measured between 0.4 and 2.4V

[4]

REF, KBDCLK, USBCLK

Fall Time

Measured between 2.4 and 0.4V

[4]

CPUCLK

CPU-CPU Clock Skew

Measured at 1.5V

250

[4]

PCICLK

PCI-PCI Clock Skew

Measured at 1.5V

250

[4]

CPUCLK, PCICLK

CPU-PCI Skew

Measured at 1.5V (

1 option)

Measured at 1.5V (

2 option)

500

[4]

CPUCLK

Cycle-Cycle Clock Jitter CPU Clock Jitter

200

Switching Waveforms

Duty Cycle Timing

1.5V

All Outputs Rise/Fall Time

OUTPUT

3.3V

0.4V

2.4V

0.4V

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