Pentium
/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs
with Intel
82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
CY2273A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07214 Rev. *A
Revised December 7, 2002
3A
Features
Mixed 2.5V and 3.3V operation
Complete clock solution for Pentium
, Pentium
II,
Cyrix, and AMD processor-based motherboards
-- Four CPU clocks at 2.5V or 3.3V
-- Up to twelve 3.3V SDRAM clocks
-- Seven synchronous PCI clocks, one free-running
-- One 3.3V 48-MHz USB clock
-- One 2.5V IOAPIC clock (-3 option only)
-- Two AGP clocks at 60 or 66.6 MHz (-2 option only)
-- One 3.3V Ref. clock at 14.318 MHz
SPI Serial Configuration Interface
Factory-EPROM programmable output drive and slew
rate for EMI customization
Factory-EPROM programmable CPU clock frequencies
for custom configurations
Power-down, CPU stop and PCI stop pins
Available in space-saving 48-pin SSOP package
Functional Description
The CY2273A is a clock synthesizer/driver for a Pentium, Pen-
tium II, Cyrix, or AMD processor-based PC using Intel's
82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.
The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with
up to 83.3MHz operation. There are seven PCI clocks, running
at 30 and 33.3MHz. One of the PCI clocks is free-running.
Additionally, the part outputs up to twelve 3.3V SDRAM clocks,
one 3.3V USB clock at 48 MHz, and one 3.3V reference clock
at 14.318 MHz. The CY2273A-2 is similar, except that
PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3
is more suited to Pentium II systems, as it outputs one 2.5V
IOAPIC clock. Finally, the CY2273A-4 is similar to the
CY2273A-1 except that is supports 0-ns CPU-PCI delay.
The CY2273A possesses power-down, CPU stop, and PCI
stop pins for power management control. These inputs are
multiplexed with SDRAM clock outputs, and are selected
when the MODE pin is driven LOW. Additionally, the signals
are synchronized on-chip, and ensure glitch-free transitions on
the outputs. When the CPU_STOP input is asserted, the CPU
clock outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all out-
puts are driven LOW.
The CY2273A outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2273A Selector Guide
Note:
1.
One free-running PCI clock.
Clocks Outputs
-1
-2
-3
-4
CPU (60, 66.6, 75,
83.3 MHz)
4
4
--
4
CPU (60, 66.6 MHz)
--
--
4
--
SDRAM
9/12
9/12
9/12
9/12
PCI (30, 33.3 MHz)
7
[1]
5
[1]
7
[1]
7
[1]
USB/IR (48 MHz)
1
1
1
1
AGP (60 or 66 MHz)
--
2
--
--
IOAPIC (14.318 MHz)
--
--
1
--
Ref (14.318 MHz)
1
1
1
1
CPU-PCI delay
15.5 ns
15.5 ns
0 ns
0 ns
Intel and Pentium are registered trademarks of Intel Corporation.
Logic Block Diagram
IOAPIC
V
DDQ2
CY2273A-3 only
EPROM
XTALOUT
XTALIN
14.318
MHz
OSC.
SDRAM [0-4],[8-11]
SEL0
SDRAM7/PCI_STOP
CPU
PLL
MODE
SCLK
SDATA
REF0 (14.318 MHz)
CPUCLK [0-3]
V
DDCPU
SDRAM6/CPU_STOP
PCI [0-5], PCI [0-3]
PCICLK_F
STOP
STOP
LOGIC
LOGIC
SDRAM5/PWR_DWN
SEL1
USBCLK (48 MHz)
SYS PLL
AGP [0,1]
INTERFACE
CONTROL
LOGIC
SERIAL
/1 or /2
CY2273A-1,-2,-4 only
CY2273A-2 only
/1 or /1.25
Delay (-1,-2 option)
CY2273A
Document #: 38-07214 Rev. *A
Page 2 of 16
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
AV
DD
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF0
V
SS
XTALIN
XTALOUT
PCICLK_F
V
DDQ3
PCICLK0
PCICLK1
V
SS
PCICLK2
PCICLK3
AGP0
AGP1
V
DDQ3
SDRAM11
SDRAM10
V
DDQ3
SDRAM9
SDRAM8
V
SS
SDATA
SCLK
V
DDQ3
USBCLK
SEL1
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM5/PWR_DWN
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
V
SS
SEL0
MODE
V
DDQ3
SDRAM4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
USBCLK
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF0
V
SS
XTALIN
XTALOUT
PCICLK_F
V
DDQ3
PCICLK0
PCICLK1
V
SS
PCICLK2
PCICLK3
PCICLK4
PCICLK5
V
DDQ3
SDRAM11
SDRAM10
V
DDQ3
SDRAM9
SDRAM8
V
SS
AV
DD
SDATA
V
DDQ2
IOAPIC
SEL0
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM5/PWR_DWN
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
V
SS
MODE
SCLK
V
DDQ3
SDRAM4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
AV
DD
34
SSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF0
V
SS
XTALIN
XTALOUT
PCICLK_F
V
DDQ3
PCICLK0
PCICLK1
V
SS
PCICLK2
PCICLK3
PCICLK4
PCICLK5
V
DDQ3
SDRAM11
SDRAM10
V
DDQ3
SDRAM9
SDRAM8
V
SS
SDATA
SCLK
V
DDQ3
USBCLK
SEL1
V
SS
CPUCLK0
CPUCLK1
V
DDCPU
CPUCLK2
CPUCLK3
V
SS
SDRAM0
SDRAM1
V
DDQ3
SDRAM2
SDRAM3
V
SS
SDRAM5/PWR_DWN
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
V
SS
SEL0
MODE
V
DDQ3
SDRAM4
V
SS
CY2273A-1,-4
CY2273A-2
CY2273A-3
SSOP
Top View
SSOP
Top View
CY2273A
Document #: 38-07214 Rev. *A
Page 3 of 16
Pin Summary
Name
Pins (-1, -4)
Pins (-2)
Pins (-3)
Description
V
DDQ3
6, 14, 19, 30, 36,
48
6, 14, 19, 30, 36,
48
6, 14, 19, 30, 36
3.3V Digital voltage supply
V
DDQ2
N/A
N/A
48
IOAPIC Digital voltage supply, 2.5V
V
DDCPU
42
42
42
CPU Digital voltage supply, 2.5V or 3.3V
AV
DD
1
1
23
Analog voltage supply, 3.3V
V
SS
3, 9, 16, 22, 27,
33, 39, 45
3, 9, 16, 22, 27,
33, 39, 45
3, 9, 16, 22, 27,
33, 39, 45
Ground
XTALIN
[2]
4
4
4
Reference crystal input
XTALOUT
[2]
5
5
5
Reference crystal feedback
SDRAM7/
PCI_STOP
28
28
28
SDRAM clock output. Also, active low control input
to stop PCI clocks, enabled when MODE is LOW.
SDRAM6/
CPU_STOP
29
29
29
SDRAM clock output. Also, active low control input
to stop CPU clocks, enabled when MODE is LOW.
SDRAM5/
PWR_DWN
31
31
31
SDRAM clock output. Also, active low control input
to power down device, enabled when MODE is LOW.
SDRAM[0:4],
[8:11]
38, 37, 35, 34,
32, 21, 20, 18, 17
38, 37, 35, 34,
32, 21, 20, 18, 17
38, 37, 35, 34,
32, 21, 20, 18, 17
SDRAM clock outputs
SEL0
26
26
46
CPU frequency select input, bit 0 (See table below.)
SEL1
46
46
N/A
CPU frequency select input, bit 0 (See table below.)
CPUCLK[0:3]
44, 43, 41, 40
44, 43, 41, 40
44, 43, 41, 40
CPU clock outputs
PCICLK[0:5] or
PCICLK[0:3]
8, 10, 11, 12, 13,
15
8, 10, 11, 12
8, 10, 11, 12, 13,
15
PCI clock outputs, at 30 or 33.33 MHz
PCICLK_F
7
7
7
Free-running PCI clock output
AGPCLK[0:1]
N/A
13, 15
N/A
AGP clock outputs at 60 or 66.66 MHz
IOAPIC
N/A
N/A
47
IOAPIC clock output
REF0
2
2
2
3.3V Reference clock output
USBCLK
47
47
1
USB Clock output at 48 MHz
SDATA
23
23
24
Serial data input for serial configuration port
SCLK
24
24
25
Serial clock input for serial configuration port
MODE
25
25
26
Mode Select pin for enabling power management
features
Function Table (-1, -2 and -4)
SEL1
SEL0
CPU/PCI
Ratio
CPUCLK[0:3]
SDRAM[0:11]
PCICLK[0:5]
PCICLK_F
AGP
(-2 Only)
REF0
IOAPIC
USBCLK
0
0
2
60.0 MHz
30.0 MHz
60.0 MHz
14.318 MHz
48 MHz
0
1
2
66.67 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
1
0
2.5
75.0 MHz
30.0 MHz
60.0 MHz
14.318 MHz
48 MHz
1
1
2.5
83.33 MHz
33.33 MHz
66.66 MHz
14.318 MHz
48 MHz
Function Table (-3)
SEL0
CPU/PCI Ratio
CPUCLK[0:3]/SDRAM[0:11]
PCICLK[0:5],PCICLK_F
REF0/IOAPIC
USBCLK
0
2
60.0 MHz
30.0 MHz
14.318 MHz
48 MHz
1
2
66.67 MHz
33.33 MHz
14.318 MHz
48 MHz
Note:
2.
For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
CY2273A
Document #: 38-07214 Rev. *A
Page 4 of 16
Output impedance: 25
(typical) measured at 1.5V
Serial Configuration Map
The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to "0".
SPI Address for the CY2273 is:
Actual Clock Frequency Values
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
CPUCLK
66.67
66.654
195
CPUCLK
60.0
60.0
0
CPUCLK
75.0
75.0
0
CPUCLK
83.33
83.138
1947
USBCLK
48.0
48.008
167
Power Management Logic
[3]
- Active when MODE pin is held `LOW'
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Stopped
Stopped
Off
Off
0
0
1
Low
Low
Running
Running
Running Running
0
1
1
Low
33/30 MHz
Running
Running
Running Running
1
0
1
60/66/75/83 MHz
Low
Running
Running
Running Running
1
1
1
60/66/75/83 MHz
30/33/30/33 MHz
Running
Running
Running Running
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
Bit 7 --
(Reserved) drive to `0'
Bit 6 --
(Reserved) drive to `0'
Bit 5 --
(Reserved) drive to `0'
Bit 4 --
(Reserved) drive to `0'
Bit 3 --
(Reserved) drive to `0'
Bit 2 --
(Reserved) drive to `0'
Bit 1
Bit 0
--
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Select Functions
Functional Description
Outputs
-2 only
CPU
PCI, PCI_F
SDRAM
Ref
IOAPIC
USBCLK
AGP
Three-State
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Test Mode
[5]
TCLK/2
[4]
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/2
TCLK/2
Notes:
3.
AGP clocks are driven on PCICLK5 and PCICLK4 on the -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and
stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
4.
TCLK supplied on the XTALIN pin in Test Mode.
5.
Valid only for SEL1 = 0.
CY2273A
Document #: 38-07214 Rev. *A
Page 5 of 16
Byte 1: CPU Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
47 (-1,-2, and -4)
1 (-3 only)
USBCLK
Bit 6
N/A
(Reserved) drive to `0'
Bit 5
N/A
(Reserved) drive to `0'
Bit 4
N/A
Not used - drive to `0'
Bit 3
40
CPUCLK3 (Active/Inactive)
Bit 2
41
CPUCLK2 (Active/Inactive)
Bit 1
43
CPUCLK1 (Active/Inactive)
Bit 0
44
CPUCLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
28
SDRAM7 (Active/Inactive)
Bit 6
29
SDRAM6 (Active/Inactive)
Bit 5
31
SDRAM5 (Active/Inactive)
Bit 4
32
SDRAM4 (Active/Inactive)
Bit 3
34
SDRAM3 (Active/Inactive)
Bit 2
35
SDRAM2 (Active/Inactive)
Bit 1
37
SDRAM1 (Active/Inactive)
Bit 0
38
SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
N/A
(Reserved) drive to `0'
Bit 6
N/A
(Reserved) drive to `0'
Bit 5
N/A
(Reserved) drive to `0'
Bit 4
47
IOAPIC (Active/Inactive) (-3 only)
Bit 3
N/A
(Reserved) drive to `0'
Bit 2
N/A
(Reserved) drive to `0'
Bit 1
N/A
(Reserved) drive to `0'
Bit 0
2
REF0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
--
(Reserved) drive to `0'
Bit 6
7
PCICLK_F (Active/Inactive)
Bit 5
15
PCICLK5 (Active/Inactive) (-1,-3 and -4)
AGP1 (Active/Inactive) (-2 only)
Bit 4
13
PCICLK4 (Active/Inactive) (-1,-3 and -4)
AGP0 (Active/Inactive) (-2 only)
Bit 3
12
PCICLK3 (Active/Inactive)
Bit 2
11
PCICLK2 (Active/Inactive)
Bit 1
10
PCICLK1 (Active/Inactive)
Bit 0
8
PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Bit 7
N/A
Not used - drive to `0'
Bit 6
N/A
Not used - drive to `0'
Bit 5
N/A
Not used - drive to `0'
Bit 4
N/A
Not used - drive to `0'
Bit 3
17
SDRAM11
Bit 2
18
SDRAM10
Bit 1
20
SDRAM9
Bit 0
21
SDRAM8
Byte 6: Reserved, for future use
PDF 
ZIP