PRELIMINARY

Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for

Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs

CY2283

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

October 12, 1998

Features

· Mixed 2.5V and 3.3V operation
· Complete clock solution for Pentium® /II, Cyrix 6x86,

and AMD K6 processor-based motherboards

-- Four CPU clocks at 2.5V or 3.3V
-- Twelve 3.3V SDRAM clocks

[1]

-- Five synchronous PCI clocks, one free-running
-- One 3.3V 48 MHz USB clock
-- One 3.3V Ref. clock at 14.318 MHz
-- Two AGP clocks at 3.3V

· Support for ALI (-1 option) and VIA (-2 option)
· I

CTM Serial Configuration Interface

· Full EMI control with factory-EPROM programmable

output drive and slew rate

· Factory-EPROM programmable CPU clock frequencies

for custom configurations

· Power-down, CPU stop, and PCI stop pins
· Available in space-saving 48-pin SSOP package

Functional Description

The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,
or AMD processor-based PCs using the ALI Aladdin V (-1 op-
tion) or VIA MVP3 (-2 option) chipset.

The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There
are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI
clocks is free-running. Additionally, the part outputs twelve
3.3V SDRAM clocks

[1]

, one 3.3V USB clock at 48 MHz, and

one 3.3V reference clock at 14.318 MHz. Finally, the part out-
puts two AGP clocks running at 66.66 MHz or 60 MHz.

The CY2283 has the flexibility to work as either a one-chip or
as part of a two-chip clocking solution. In 100-MHz board de-
signs based on the ALI Aladdin V chipset, it is recommended
that the CY2283 be used with an external SDRAM buffer so-
lution such as the CY2318NZ or CY2314NZ. In this configura-
tion the SDRAM outputs on the CY2283 must be either turned
off using I

C or left floating. The CY231xNZ family provides the

SDRAM outputs in place of the CY2283 and can be placed in
close proximity to the SDRAM modules.

The CY2283 possesses power-down, CPU stop, and PCI stop
pins for power management control. These inputs are multi-
plexed with SDRAM clock outputs, and are selected when the
MODE pin is driven LOW. Additionally, the signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.

The CY2283 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.

CY2283 Selector Guide

Notes:

SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the
ALI V chipset, an external CY231xNZ buffer should be used.

One free-running PCI clock

Clock Outputs

-1 (ALI V)

-2 (VIA MVP3)

CPU (66.6, 75, 83.3, 100MHz)

SDRAM

[1]

PCI (30, 33.3 MHz)

[2]

USB (48MHz)

AGP (66.6, 60MHz)

Ref. (14.318 MHz)

CPU-PCI delay

2.5

5.5 ns

2.5

5.5 ns

AGP clock

In phase

with PCI

In phase

with CPU

Pin Configuration (48 SSOP)

Logic Block Diagram

EPROM

XTALOUT

XTALIN

14.318

MHz

OSC.

SDRAM [0-4],[8-11]

SEL0

SDRAM7/PCI_STOP

CPU

PLL

MODE

SCLK

SDATA

REF0 (14.318 MHz)

CPUCLK [0-3]

DDCPU

SDRAM6/CPU_STOP

PCI [0-3]

PCICLK_F

STOP

LOGIC

SDRAM5/PWR_DWN

SEL1

USBCLK

SYS PLL

10
11

2283-

1,-

REF0

XTALIN

XTALOUT

PCICLK_F

DDQ3

PCICLK0

PCICLK1

PCICLK2

PCICLK3

AGP0

AGP1

DDQ3

SDRAM11

SDRAM10

DDQ3

SDRAM9

SDRAM8

SDATA

SCLK

DDQ3

USBCLK

SEL1

CPUCLK0

CPUCLK1
V

DDCPU

CPUCLK2

CPUCLK3

SDRAM0

SDRAM1
V

DDQ3

SDRAM2

SDRAM3

SDRAM5/PWR_DWN

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

SEL0

MODE

DDQ3

SDRAM4

AGP

INTERFACE

CONTROL

LOGIC

SERIAL

Delay (-1 option)

Delay (-2 option)

/1, /1.25, /1.5

CY2283

PRELIMINARY

Pin Summary

Name

Pins

Description

DDQ3

6, 14, 19, 30, 36, 48 3.3V Digital voltage supply

DDCPU

CPU Digital voltage supply, 2.5V or 3.3V

Analog voltage supply, 3.3V

3, 9, 16, 22, 27, 33,
39, 45

Ground

XTALIN

[3]

Reference crystal input

XTALOUT

[3]

Reference crystal feedback

SDRAM7/ PCI_STOP

SDRAM clock output. Also, active LOW control input to stop PCI clocks, enabled
when MODE is LOW.

SDRAM6/CPU_STOP

SDRAM clock output. Also, active LOW control input to stop CPU clocks, enabled
when MODE is LOW.

SDRAM5/ PWR_DWN

SDRAM clock output. Also, active LOW control input to power down device,
enabled when MODE is LOW.

SDRAM[0:4],[8:11]

38, 37, 35, 34, 32,
21, 20, 18, 17

SDRAM clock outputs

SEL0

CPU frequency select input, bit 0 (see table below)

SEL1

CPU frequency select input, bit 0 (see table below)

CPUCLK[0:3]

44, 43, 41, 40

CPU clock outputs

PCICLK[0:3]

8, 10, 11, 12

PCI clock outputs, at one-half the CPU frequency.

PCICLK_F

Free-running PCI clock output

AGP[0:1]

13, 15

AGP clock outputs

REF0

3.3V Reference clock output

USBCLK

USB Clock output

SDATA

Serial data input for serial configuration port

SCLK

Serial clock input for serial configuration port

MODE

Mode Select pin for enabling power management features

Note:

For best accuracy, use a parallel-resonant crystal, C

LOAD

= 18 pF.

Function Table

SEL1

SEL0

CPU/PCI

Ratio

CPUCLK[0:3]
SDRAM[0:11]

PCICLK[0:3]

PCICLK_F

AGP[0:1]

REF0

USBCLK

2.5

83.33 MHz

33.33 MHz

66.66 MHz

14.318 MHz

48 MHz

66.67 MHz

33.33 MHz

66.66 MHz

14.318 MHz

48 MHz

3.0

100.0 MHz

33.33 MHz

66.66 MHz

14.318 MHz

48 MHz

2.5

75.0 MHz

30.0 MHz

60.0 MHz

14.318 MHz

48 MHz

CY2283

PRELIMINARY

CPU and PCI Clock Driver Strengths

· Matched impedances on both rising and falling edges on

the output drivers

· Output impedance: 25

(typical) measured at 1.5V

Serial Configuration Map

· The Serial bits will be read by the clock driver in the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

· Reserved and unused bits should be programmed to "0".
· I

C Address for the CY2283 is:

Actual Clock Frequency Values

Clock Output

Target

Frequency

(MHz)

Actual

Frequency

(MHz)

PPM

CPUCLK

66.67

66.51

2346

CPUCLK

75.0

CPUCLK

83.33

83.14

-2346

CPUCLK

100.0

99.77

-2346

USBCLK

48.0

48.01

167

Power Management Logic

[4]

- Active when MODE pin is held `LOW'

CPU_STOP

PCI_STOP

PWR_DWN

CPUCLK

PCICLK

PCICLK_F

Other

Clocks

Osc.

PLLs

Low

Stopped

Off

Low

Running

Low

33/30 MHz

Running

66/75/83/100MHz

Low

Running

66/75/83/100MHz

30/33.3 MHz

Running

R/W

----

Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)

Bit

Pin #

Description

Bit 7

(Reserved) drive to `0'

Bit 6

(Reserved) drive to `0'

Bit 5

(Reserved) drive to `0'

Bit 4

(Reserved) drive to `0'

Bit 3

(Reserved) drive to `0'

Bit 2

(Reserved) drive to `0'

Bit 1
Bit 0

Bit 1
1
1
0
0

Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation

Select Functions

Functional Description

Outputs

CPU

PCI, PCI_F

SDRAM

Ref

IOAPIC

USBCLK

AGP

Three-State

Hi-Z

Test Mode

[6]

TCLK/2

[5]

TCLK/4

TCLK/2

TCLK

TCLK/2

Notes:

AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.

TCLK supplied on the XTALIN pin in Test Mode.

Valid only for SEL1=0.

CY2283

PRELIMINARY

Byte 1: CPU Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

USBCLK

Bit 6

N/A

(Reserved) drive to `0'

Bit 5

N/A

(Reserved) drive to `0'

Bit 4

N/A

Not used - drive to `0'

Bit 3

CPUCLK3 (Active/Inactive)

Bit 2

CPUCLK2 (Active/Inactive)

Bit 1

CPUCLK1 (Active/Inactive)

Bit 0

CPUCLK0 (Active/Inactive)

Byte 3: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

SDRAM7 (Active/Inactive)

Bit 6

SDRAM6 (Active/Inactive)

Bit 5

SDRAM5 (Active/Inactive)

Bit 4

SDRAM4 (Active/Inactive)

Bit 3

SDRAM3 (Active/Inactive)

Bit 2

SDRAM2 (Active/Inactive)

Bit 1

SDRAM1 (Active/Inactive)

Bit 0

SDRAM0 (Active/Inactive)

Byte 5: Peripheral Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

N/A

(Reserved) drive to `0'

Bit 6

N/A

(Reserved) drive to `0'

Bit 5

N/A

(Reserved) drive to `0'

Bit 4

N/A

(Reserved), drive to `0'

Bit 3

N/A

(Reserved) drive to `0'

Bit 2

N/A

(Reserved) drive to `0'

Bit 1

N/A

(Reserved) drive to `0'

Bit 0

REF0 (Active/Inactive)

Byte 2: PCI Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

(Reserved) drive to `0'

Bit 6

PCICLK_F (Active/Inactive)

Bit 5

AGP1 (Active/Inactive)

Bit 4

AGP0 (Active/Inactive)

Bit 3

PCICLK3 (Active/Inactive)

Bit 2

PCICLK2 (Active/Inactive)

Bit 1

PCICLK1 (Active/Inactive)

Bit 0

PCICLK0 (Active/Inactive)

Byte 4: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

N/A

Not used - drive to `0'

Bit 6

N/A

Not used - drive to `0'

Bit 5

N/A

Not used - drive to `0'

Bit 4

N/A

Not used - drive to `0'

Bit 3

SDRAM11

Bit 2

SDRAM10

Bit 1

SDRAM9

Bit 0

SDRAM8

Byte 6: Reserved, for future use

CY2283

PRELIMINARY

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ..................................................0.5 to +7.0V

Input Voltage .............................................. 0.5V to V

+0.5

Storage Temperature (Non-Condensing) ... 65

C to +150

Max. Soldering Temperature (10 sec) ...................... +260

Junction Temperature ............................................... +150

Package Power Dissipation .............................................. 1W

Static Discharge Voltage ........................................... >2000V
(per MIL-STD-883, Method 3015, like V

pins tied together)

Operating Conditions

[7]

Parameter

Description

Min.

Max.

Unit

, V

DDQ3

Analog and Digital Supply Voltage

3.135

3.465

DDCPU

CPU Supply Voltage

2.375
3.135

2.9

3.465

Operating Temperature, Ambient

Max. Capacitive Load on

CPUCLK, USBCLK, IOAPIC
PCICLK, AGP, SDRAM
REF0

10
20
20

20
30
45

(REF)

Reference Frequency, Oscillator Nominal Value

14.318

MHz

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Except Crystal Inputs

2.0

Low-level Input Voltage

Except Crystal Inputs

0.8

ILiic

Low-level Input Voltage

C inputs only

0.7

High-level Output Voltage

DDCPU

= V

DDQ2

= 2.375V

= 16 mA CPUCLK

2.0

= 18 mA IOAPIC

Low-level Output Voltage

DDCPU

= V

DDQ2

= 2.375V

= 27 mA

CPUCLK

0.4

= 29 mA

IOAPIC

High-level Output Voltage

DDQ3

, AV

, V

DDCPU

= 3.135V

= 16 mA CPUCLK

2.4

= 36 mA SDRAM

= 32 mA PCICLK

= 26 mA USBCLK

= 36 mA REF0

Low-level Output Voltage

DDQ3

, AV

, V

DDCPU

= 3.135V

= 27 mA

CPUCLK

0.4V

= 29 mA

SDRAM

= 26 mA

PCICLK

= 21 mA

USBCLK

= 29 mA

REF0

Input High Current

= V

+10

Input Low Current

= 0V

Output Leakage Current

Three-state

+10

Power Supply Current

[8]

= 3.465V, V

= 0 or V

, Loaded Outputs,

CPU clocks = 66.67 MHz

300

Power Supply Current

[8]

= 3.465V, V

= 0 or V

, Unloaded Outputs

120

DDS

Power-down Current

Current draw in power-down state

500

Notes:

Electrical parameters are guaranteed with these operating conditions.

Power supply current will vary with number of outputs that are running.

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