100-MHz Spread Spectrum Clock Synthesizer/Driver with

USB, Hublink, and SDRAM Support

CY2287

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

June 23, 1999

Features

Benefits

· Mixed 2.5V and 3.3V Operation

Usable with Pentium

II, K6, and 6x86 Processors

· Multiple output clocks at different frequencies

-- Three CPU clocks at 2.5V, up to 100 MHz
-- Nine 3.3V SDRAM clocks at 100 MHz
-- Eight synchronous PCI clocks at 33 MHz
-- Two synchronous APIC clocks at 16.67 MHz or 33

MHz

-- Two 3V66 clocks at 66 MHz
-- Two USB clocks at 48 MHz
-- One reference clock at 14.318 MHz

Single-chip main motherboard clock generator

-- High-Speed Processor Support
-- Supports Two 4-Clock SDRAM DIMMs
-- Support for Six PCI Slots
-- Synchronous to the CPU Clock
-- Hublink Support
-- Universal Serial Bus Support
-- Also used as an input strap to determine APIC frequency

· Spread Spectrum clocking

-- 31 kHz modulation frequency
-- EPROM programmable percentage of spreading
-- Default is 0.6%, which is recommended by Intel®
-- Additional options of 0.25% and 0.4% available

Enables reduction of EMI

· Power-down features

Supports mobile systems

· I

CTM Interface

Dynamic output control

· Low skew and low jitter outputs

Meets tight system timing requirements at high frequency

· Test Mode

Enables ATE and "bed of nails" testing

· 56-pin SSOP package

Widely available, standard package enables lower cost

Intel and Pentium are registered trademarks of Intel Corporation.
I

C is a trademark of Philips Corporation.

SERIAL INTERFACE

CONTROL LOGIC

Logic Block Diagram

EPROM

XTALOUT

XTALIN

APIC [01] (16.67/33MHz)

14.318

MHz

OSC.

SDRAM [0-8] (100 MHz)

SEL1

CPU

PLL

REF0/SEL33 (14.318 MHz)

CPU [02] (66/100 MHz)

PCI [07] (33MHz)

SYS

PLL

USB [01] (48MHz)

EPROM

Configurable

Logic

PWR_DWN

3V66 [01] (66MHz)

SSOP

Top View

REF0/SEL33

DDREF

XTAL_IN

XTAL_OUT

DDPCI

SSPCI

SCLK

SDRAM8

SDRAM4

SSSDRAM

DDAPIC

3V66_0

PCI3

PCI7

USB1

SDRAM6

SDRAM2

CPU1

SSAPIC

SSREF

SS3V66

3V66_1

DD3V66

PCI0

PCI1

PCI2

SSPCI

PCI4

PCI5

PCI6

DDPCI

SSUSB

USB0

DDSDRAM

PWRDWN

SSSDRAM

SDRAM7

DDSDRAM

SDRAM5

SSSDRAM

SDRAM3

DDSDRAM

SDRAM1

SDRAM0

SSCPU

CPU2

DDCPU

CPU0

APIC1

APIC0

DDUSB

SEL0

SDATA

SEL1

CY2287

SCLK

SDATA

SEL0

CY2287

Pin Summary

Name

Pins

Description

REF/SEL33

3.3V 14.31818-MHz clock output and power-on external select strap op-
tion for APIC clock frequency.
Strap LOW: APIC = PCI/2
Strap HIGH: APIC = 33.3 MHz

XTAL_IN

[1]

14.31818-MHz crystal input

XTAL_OUT

[1]

14.31818-MHz crystal output

PCI [07]

11, 12, 13, 15, 16, 18, 19, 20

3.3V PCI clock outputs

3V66 [01]

7, 8

3.3V Fixed 66.67-MHz clock outputs

USB [01]

25, 26

3.3V Fixed 48-MHz clock outputs

SEL [01]

28, 29

3.3V LVTTL compatible inputs for logic selection

PWRDWN

3.3V LVTTL compatible input. Device enters powerdown mode when held
LOW

CPU [02]

49, 50, 52

2.5V 66.67-MHz or 100-MHz (selectable) host bus clock output

SDRAM [08]

35, 36, 37, 39, 40, 42, 43, 45, 46 3.3V SDRAM clock outputs running 100 MHz

APIC [01]

54, 55

2.5V APIC clock outputs running synchronous with PCI clock frequency.
Selectable 16.67 MHz or 33.3 MHz

SDATA

C compatible SDATA input

SCLK

C compatible SCLK input

DDREF

3.3V Power supply for REF output

SSREF

REF ground

SS3V66

3V66 Ground

DD3V66

3.3V Power supply for 3V66 outputs

DDPCI

10, 21

3.3V Power supply for PCI outputs

SSPCI

14, 17

PCI ground

3.3V Analog power supply

Analog ground

SSUSB

USB ground

DDUSB

3.3V Power supply for USB outputs

DDSDRAM

33, 38, 44

3.3V Power supply for SDRAM outputs

SSSDRAM

35, 41, 47

SDRAM ground

SSCPU

CPU ground

DDCPU

2.5V Power supply for CPU outputs

DDAPIC

2.5V Power supply for APIC outputs

SSAPIC

APIC ground

Note:

For best accuracy, use a parallel-resonant crystal, C

LOAD

= 18 pF. For crystals with different C

LOAD

, please refer to the application note, "Crystal Oscillator

Topics."

CY2287

Function Table

SEL2

[2]

SEL1

SEL0

CPU

(MHz)

SDRAM

(MHz)

3V66

(MHz)

PCI

(MHz)

USB

(MHz)

REF

(MHz)

APIC

[4]

(MHz)

APIC

[5]

(MHz)

Hi-Z

TCLK

[3]

TCLK/2

TCLK/3

TCLK/8

TCLK/2

TCLK

TCLK/16

TCLK/8

66.67

100

66.67

33.33

14.318

16.67

33.33

100

66.67

33.33

14.318

16.67

33.33

66.67

100

66.67

33.33

14.318

16.67

33.33

100

66.67

33.33

14.318

16.67

33.33

66.67

100

66.67

33.33

14.318

16.67

33.33

100

66.67

33.33

14.318

16.67

33.33

Spread Spectrum

[2]

SEL2

[2]

SEL1

SEL0

Spread Spectrum Margin

N/A

0.6%

0.25%

0.4%

Actual Clock Frequency Values

Clock Output

Target

Frequency (MHz)

Actual

Frequency (MHz)

PPM

CPUCLK

66.67

66.288

5230

CPUCLK

100.0

99.432

5680

USBCLK

48.0

48.008

+167

Notes:

Not a dedicated input pin. This selection must be addressed via I

C interface.

TCLK supplied on the XTALIN pin in Test Mode.

SEL33 = LOW (power-on latch input).

SEL33 = HIGH (power-on latch input).

CY2287

Serial Configuration Map

· The Serial bits will be read by the clock driver in the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

· Reserved and unused bits must be programmed to "0".
· I

C Address for the CY2287 is:

R/W

Byte 0: Spread Spectrum, USB, SDRAM8
Control Register
(1 = Enable, 0 = Disable)
Default = Enable (for Bit [0:2])
Default = Disable (for Bit [3:7])

Bit

Pin #

Description

Bit 7 --

Reserved

Bit 6 --

Reserved

Bit 5 --

Reserved

Bit4

SEL2

Bit3

Spread Spectrum (Default = Disable)

Bit2

USB1

Bit1

USB0

Bit0

CPU2

Byte 1: SDRAM Control Register
(1 = Enable, 0 = Disable)
Default = Enable

Bit

Pin #

Description

Bit 7

SDRAM7

Bit 6

SDRAM6

Bit 5

SDRAM5

Bit 4

SDRAM4

Bit 3

SDRAM3

Bit 2

SDRAM2

Bit 1

SDRAM1

Bit 0

SDRAM0

Byte 2: PCI Control Register
(1 = Enable, 0 = Disable)
Default = Enable (for Bit [1:7])
Default = Disable (for Bit 0)

Bit

Pin #

Description

Bit 7

PCI7

Bit 6

PCI6

Bit 5

PCI5

Bit 4

PCI4

Bit 3

PCI3

Bit 2

PCI2

Bit 1

PCI1

Bit 0

Reserved

Byte 3: Peripheral Control Register
(0 = Enable, 1 = Disable)
Default = Enable

Bit

Pin #

Description

Bit 7

3V66_1

Bit 6

3V66_0

Bit 5

PCI0

Bit 4

SDRAM8

Bit 3

APIC1

Bit 2

APIC0

Bit 1

CPU1

Bit 0

CPU0

Byte 4: Reserved Register
(0 = Enable, 1 = Disable)
Default = Disable

Bit

Pin #

Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

CY2287

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ..................................................0.5 to +7.0V

Input Voltage .............................................. 0.5V to V

+0.5

Storage Temperature (Non-Condensing) ... 65°C to +150°C

Max. Soldering Temperature (10 sec) ...................... +260°C

Junction Temperature ............................................... +150°C

Package Power Dissipation .............................................. 1W

Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V

Operating Conditions

Over Which Electrical Parameters are Guaranteed

Parameter

Description

Min.

Max.

Unit

DD3.3V

3.3V Supply Voltages

3.135

3.465

DD2.5V

2.5V Supply Voltages

2.375

2.625

Operating Temperature, Ambient

°C

Max. Capacitive Load on

CPU, USB, REF, APIC
SDRAM, PCI, 3V66

20
30

(REF)

Reference Frequency, Oscillator Nominal Value

14.318

MHz

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min.

Typ

Max. Unit

High-level Input Voltage

All inputs except SCLK/SDATA and crystal inputs

[6]

2.0

SCLK/SDATA

0.7

Low-level Input Voltage

All inputs except SCLK/SDATA and crystal inputs

[6]

0.8

SCLK/SDATA

0.3

Input High Current

0 < V

< V

+10

Input Low Current

0 < V

< V

+10

High-level Output Current

CPU

= 2.0V

-60

USB, REF

= 2.4V

SDRAM

= 2.4V

100

PCI, 3V66

= 2.4V

100

APIC

= 2.0V

-60

Low-level Output Current

CPU

= 0.4V

USB, REF

= 0.4V

SDRAM

= 0.4V

PCI, 3V66

= 0.4V

APIC

= 0.4V

Output Leakage Current

Three-state

DD2

2.5V Power Supply Current

DD33

= 3.465V, V

DD25

= 2.625V, F

CPU

= 100 MHz

100

DD3

3.3V Power Supply Current

DD33

= 3.465V, V

DD25

= 2.625V, F

CPU

= 100 MHz

280

DDPD2

2.5V Shutdown Current

DD33

= 3.465V, V

DD25

= 2.625V

[7]

500

DDPD3

3.3V Shutdown Current

DDQ3

= 3.465V, V

DD25

= 2.625V

[7]

500

Notes:

Crystal inputs have CMOS thresholds, nominally V

/2.

Tested @ 500

A. Actual performance is much better. Call Cypress if tighter spec is required.

CY2287

CY2287 Switching Characteristics

[8]

Over the Operating Range

Parameter

Output

Description

Test Conditions

Min.

Max.

Unit

All

Output Duty Cycle

[9]

/(t

+ t

)

CPU, APIC

Rising Edge Rate

Between 0.4V and 2.0V

1.0

4.0

V/ns

USB, REF

Rising Edge Rate

Between 0.4V and 2.4V

0.5

2.0

V/ns

PCI, 3V66

Rising Edge Rate

Between 0.4V and 2.4V

1.0

4.0

V/ns

SDRAM

Rising Edge Rate

Between 0.4V and 2.4V

1.0

4.0

V/ns

CPU, APIC

Falling Edge Rate

Between 2.0V and 0.4V

1.0

4.0

V/ns

USB, REF

Falling Edge Rate

Between 2.4V and 0.4V

0.5

2.0

V/ns

PCI, 3V66

Falling Edge Rate

Between 2.4V and 0.4V

1.0

4.0

V/ns

SDRAM

Falling Edge Rate

Between 2.4V and 0.4V

1.0

4.0

V/ns

CPU

CPU-CPU Skew

Measured at 1.25V

175

SDRAM

SDRAM-SDRAM Skew

Measured at 1.5V

250

APIC

APIC-APIC Skew

Measured at 1.25V

250

PCI

PCI-PCI Skew

Measured at 1.5V

500

3V66

3V66-3V66 Skew

Measured at 1.5V

175

3V66, PCI

3V66-PCI Clock Skew

3V66 leads

[10]

1.5

4.0

APIC, PCI

APIC-PCI Clock Skew

Coincident every edge

[10, 11]

500

SDRAM, 3V66

SDRAM-3V66 Clock Skew

Coincident every other 3V66 edge

[10]

500

6_66

CPU, 3V66

CPU-3V66 Clock Skew

CPU leads

[10]

7.0

8.0

6_100

CPU, 3V66

CPU-3V66 Clock Skew

Coincident every other 3V66 edge

[10]

500

7_66

CPU, SDRAM

CPU-SDRAM Clock Skew

SDRAM leads

[10, 12]

2.0

3.0

7_100

CPU, SDRAM

CPU-SDRAM Clock Skew

CPU leads, measured every edge

[10]

4.5

5.5

CPU

Cycle-Cycle Clock Jitter

Measured at 1.25V, t

250

SDRAM

Cycle-Cycle Clock Jitter

Measured at 1.5V, t

250

APIC

Cycle-Cycle Clock Jitter

Measured at 1.25V, t

500

USB

Cycle-Cycle Clock Jitter

Measured at 1.5V, t

500

3V66

Cycle-Cycle Clock Jitter

Measured at 1.5V, t

500

REF

Cycle-Cycle Clock Jitter

Measured at 1.5V, t

1000

STABLE

All Outputs

Settle Time

All clock stabilization from power-up

Notes:

All parameters specified with loaded outputs as follows: CPU, APIC, REF, USB = 12.5 pF: SDRAM, 3V66, PCI=20 pF.

Duty cycle is measured at 1.5V when V

= 3.3V. When V

= 2.5V, duty cycle is measured at 1.25V.

10. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks.
11. Coincident every other APIC edge if APIC running at 16 MHz.
12. Measured every third CPU edge.

CY2287

Switching Waveforms

Notes:

13. Once the PWR_DWN signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest will be held LOW on the next HIGH-to-LOW

transition.

14. Waveforms are not to scale.
15. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

Duty Cycle Timing

All Outputs Rise/Fall Time

OUTPUT

CLK-CLK Output Skew

CLKA

CLKB

Cycle-Cycle Clock Jitter

CLK

PWR_DOWN

CPUCLK

Peripheral

PWR_DWN

VCO

Crystal

Clocks

[13, 14, 15]

CY2287

Switching Waveforms

(continued)

CPU 66 MHz

SDRAM 100 MHz

3V66 66 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 66 MHz)

CPU 66 MHz

3V66 66 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

CPU to 3V66 Skew, CPU leads 3V66 by 7.5ns (500-ps window)

CLK-CLK Output Skew (CPU @ 66 MHz)

6_66

SDRAM 100 MHz

CPU 66 MHz

SDRAM 100 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

CPU to SDRAM Skew, SDRAM leads CPU by 2.5 ns (500-ps window)

3V66 66 MHz

CLK-CLK Output Skew (CPU @ 66 MHz)

7_66

CY2287

Switching Waveforms

(continued)

CPU 100 MHz

SDRAM 100 MHz

3V66 66 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 100 MHz)

CPU 100 MHz

SDRAM 100 MHz

3V66 66 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

CPU to 3V66 Skew, CPU leads 3V66 by 0.0 ns (500-ps window)

CLK-CLK Output Skew (CPU @ 100 MHz)

6_100

CPU 100 MHz

SDRAM 100 MHz

0 ns

10 ns

20 ns

30 ns

40 ns

CPU to SRAM Skew, CPU leads SDRAM by 5.0 ns (500-ps window)

3V66 66 MHz

7_100

CLK-CLK Output Skew (CPU @ 100 MHz)

CY2287

Switching Waveforms

(continued)

Group A

Group B

1.5V

Window Measurement Clarification

Example of SDRAM to 3V66 Skew Measurement (CPU @ 66 or 100 MHz)

SDRAM leads 3V66 by 0.0 ns (500-ps window)

500-ps window

Latest of Group B

Earliest of Group A

CPU Group

3V66 Group

1.5V

1.25V

Window Measurement Clarification

Example of CPU to 3V66 Skew Measurement (CPU @ 66 MHz)

CPU leads 3V66 by 7.5 ns (500-ps window)

8.0-ns window (max)

Latest of 3V66 Group

Earliest of CPU Group

Latest of CPU Group

Earliest of 3V66 Group

7.0-ns window (min)

CY2287

Application Information

Clock traces must be terminated with either series or parallel termination, as they are normally done.

Application Circuit

Summary

· A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C

LOAD

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
C

LOAD

is used. Footprints must be laid out for flexibility.

· Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 2.2 nF.

In some cases, smaller value capacitors may be required.

· The value of the series terminating resistor satisfies the following equation, where R

trace

is the loaded characteristic impedance

of the trace, R

out

is the output impedance of the clock generator (CPU/APIC = 29 Ohm, USB/REF = 40 Ohm, SDRAM (3.3V)=

16 Ohm, PCI/3V66 = 30 Ohm - all nominal driver output impedances), and R

series

is the series terminating resistor.

series

> R

trace

out

· Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

· A Ferrite Bead may be used to isolate the Board V

from the clock generator V

island. Ensure that the Ferrite Bead offers

greater than 50

impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout

and Termination Techniques for Cypress Clock Generators" for more details.

· If a Ferrite Bead is used, a 10

F 22

F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

XTALIN
XTALOUT

PWR_DWN

SEL0
SEL1

PWR_DWN

VDD3.3V

VDD2.5V

VSS

CPU

PCI

HUBLINK

SDRAM

APIC

REF
USB

CPU

PCI

3V66

SDRAM

APIC
REF
USB

CY2287-1 56 Pin SSOP

Cd = Decoupling Capacitors (

NOTE: May use 0.1

F, but value will vary with frequency of operation and output current

)

Ct = Optional EMI-Reducing Capacitors
Cx = Optional Load Matching Capacitors
Rs = Termination Resistor

3.3V VDD

2.5V VDD

SEL0
SEL1

CY2287

cy2287: May 26, 1998
Revision: June 23, 1999

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document #: 3800711A

Test Circuit

Note: All capacitors must be placed as close to the pins as is physically possible.

5, 6, 14, 17, 23, 24, 34, 41, 47, 48, 56

2, 9, 10, 21, 22, 27, 32, 38, 44

DD3.3V

LOAD

OUTPUTS

DD2.5V

CY2287

51, 53

Note: Each supply pin must have an individual decoupling capacitor.

Ordering Information

Ordering Code

Package

Name

Package Type

Operating

Range

CY2287PVC1

O56

56-Pin SSOP

Commercial

Package Diagram

56-Lead Shrunk Small Outline Package O56

51-85062-B

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY2287PVC-1

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY2287PVC-1