128-Macrocell MAX
EPLD
CY7C346B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03037 Rev. *A
Revised April 8, 2002
46B
Features
128 macrocells in eight logic array blocks (LABs)
20 dedicated inputs, up to 64 bidirectional I/O pins
Programmable interconnect array
Advanced 0.65-micron CMOS technology to increase
performance
Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
Functional Description
The CY7C346B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX
architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
The 128 macrocells in the CY7C346B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
The speed and density of the CY7C346B allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functionality
of 20-pin PLDs, the CY7C346B allows the replacement of over
50 TTL CY7C346B. By replacing large amounts of logic, the
CY7C346B reduces board space, part count, and increases
system reliability.
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
Logic Block Diagram
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 121128
MACROCELL 105112
MACROCELL 8696
MACROCELL 4148
MACROCELL 2532
MACROCELL 916
SYSTEM CLOCK
P
I
A
INPUT [59] (N4)
36
.
INPUT [60] (M5)
37
.
INPUT [61] (N5)
38
.
INPUT [64] (N6)
41
.
INPUT [65] (M7)
42
.
INPUT [66]
(L7)
43
.
INPUT [67] (N7)
44
.
INPUT [70]
(L8)
47
.
INPUT [71] (N9)
48
.
INPUT [72] (M9)
49
.
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
8 (B13)
[1]
9 (C12)
[2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11)
[6]
NC (A11) [7]
NC (B10) [8]
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2) [40]
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
LAB H
LAB G
LAB F
LAB E
LAB A
LAB B
LAB C
LAB D
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8)
[18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6)
[12, 13, 37, 38, 62, 63, 87, 88]
VCC
GND
() PERTAIN TO 100-PIN PGA PACKAGE
1 (C7) [16]
INPUT/CLK
.
78 (A10) [9]
INPUT
.
.....
79 (B9) [10]
INPUT
.
.....
80 (A9) [11]
INPUT
.....
83 (A8) [14]
INPUT
.
.....
84 (B7) [15]
INPUT
.
.....
2 (A7) [17]
INPUT
.
.....
5 (C6) [20]
INPUT
.
.....
6 (A5) [21]
INPUT
.
.....
7 (B5) [22]
INPUT
.
.....
MACROCELL 73 80
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 57 64
[ ] PERTAIN TO 100-PIN PQFP PACKAGE
.
CY7C346B
Document #: 38-03037 Rev. *A
Page 4 of 15
Logic Array Blocks
There are eight logic array blocks in the CY7C346B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Externally, the CY7C346B provides 20 dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Design Recommendations
Operation of the devices described herein with conditions
above those listed in the "Maximum Ratings" section of this
datasheet may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure
to absolute maximum ratings conditions for extended periods
of time may affect device reliability. The CY7C346B contains
circuitry to protect device pins from high static voltages or
electric fields, but normal precautions should be taken to avoid
application of any voltage higher than the maximum rated
voltages.
For proper operation, input and output pins must be
constrained to the range GND
(V
IN
or V
OUT
)
V
CC
. Unused
inputs must always be tied to an appropriate logic level
(either V
CC
or GND). Each set of V
CC
and GND pins must
be connected directly at the device. Power supply
decoupling capacitors of at least 0.2
F must be connected
between V
CC
and GND. For the most effective decoupling,
each V
CC
pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Security
The CY7C346B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
LOGIC ARRAY
CONTROL DELAY
t
LAC
EXPANDER
DELAY
t
EXP
CLOCK
DELAY
t
IC
t
RD
t
COMB
t
LATCH
INPUT
DELAY
t
IN
REGISTER
OUTPUT
DELAY
t
OD
t
XZ
t
ZX
LOGIC ARRAY
DELAY
t
LAD
FEEDBACK
DELAY
t
FD
OUTPUT
INPUT
C346B9
SYSTEM CLOCK DELAY t
ICS
t
RH
t
RSU
t
PRE
t
CLR
PIA
DELAY
t
PIA
I/O DELAY
t
IO
Figure 1. CY7C346B Internal Timing Model
CY7C346B
Document #: 38-03037 Rev. *A
Page 5 of 15
program data, may be reset simply by erasing the entire
device.
The CY7C346B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t
SU
if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, t
EXP
to t
SU
. Determine which of 1/(t
WH
+ t
WL
), 1/t
CO1
,
or 1/(t
EXP
+ t
SU
) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on the dedicated input pins.
When expander logic is used in the data path, add the
appropriate maximum expander delay, t
EXP
to t
AS1
. Determine
which of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous
configuration.
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t
OH
is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
Typical I
CC
vs. f
MAX
Output Drive Current
400
300
200
100
1 kHz
10 kHz
100 kHz
1 MHz
I
CC
MAXIMUM FREQUENCY
10 MHz
0
50 MHz
100 Hz
AC
T
I
VE
(m
A)
T
y
p.
V
CC
= 5.0V
Room Temp.
C346B10
0
1
2
3
4
I
OUT
P
UT CUR
RE
NT (
m
A
)
TY
P
I
CA
L
V
O
OUTPUT VOLTAGE (V)
250
200
150
100
50
5
O
I
OH
I
OL
V
CC
= 5.0V
Room Temp.
C346B11
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