USE ULTRA37000TM
FOR ALL NEW DESIGNS
UltraLogicTM 128-Macrocell Flash CPLD
CY7C375i
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-03029 Rev. *A
Revised May 10, 2004
Features
128 macrocells in eight logic blocks
128 I/O pins
Five dedicated inputs including 4 clock pins
In-System Reprogrammable (ISRTM) Flash technology
-- JTAG Interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
-- f
MAX
= 125 MHz
-- t
PD
= 10 ns
-- t
S
= 5.5 ns
-- t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370iTM family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C375i is
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogicTM F
LASH
370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Logic Block Diagram
PIM
INPUT
MACROCELL
Clock
Inputs
4
4
36
16
16
36
LOGIC
BLOCK
36
16
16
36
16 I/Os
36
36
36
16
16
36
16
16
64
64
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
I/O
15
A
Inputs
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
16
I/O
31
I/O
32
I/O
47
I/O
48
I/O
63
I/O
112
I/O
127
I/O
96
I/O
111
I/O
80
I/O
95
I/O
64
I/O
79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
Selection Guide
7C375i125 7C375i100 7C375i83 7C375iL83 7C375i66 7C375iL66 Unit
Maximum Propagation Delay
[1]
, t
PD
10
12
15
15
20
20
ns
Minimum Set-Up, t
S
5.5
6
8
8
10
10
ns
Maximum Clock to Output
[1]
, t
CO
6.5
7
8
8
10
10
ns
Typical Supply Current, I
CC
125
125
125
75
125
75
mA
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V
USE ULTRA37000TM
FOR ALL NEW DESIGNS
CY7C375i
Document #: 38-03029 Rev. *A
Page 2 of 17
Pin Configurations
I/O
2
12
4
3
12
3
4
12
2
5
12
1
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
16
0
45
15
9
46
15
8
47
15
7
48
15
6
49
15
5
50
15
4
51
15
3
52
15
2
53
15
1
54
15
0
55
14
9
56
14
8
57
14
7
58
14
6
59
14
5
60
14
4
61
14
3
62
14
2
63
14
1
64
65
66
67
68
14
0
69
13
9
70
13
8
71
13
7
72
13
6
73
13
5
74
13
4
75
13
3
76
13
2
77
13
1
78
13
0
79
12
9
80
12
8
81
12
7
82
12
6
TQFP
Top View
12
5
84
83
42
1
GND
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
/SCLK
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
GND
CLK
0
/I
0
V
CCIO
GND
CLK
1
/I
1
GND
GND
48
GND
2
CC
I
O
GND
GND
V
CCIO
I/O
49
I/O
50
I/O
51
I/O
52
I/
O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
I
V
CCINT
V
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O
CCIO
V
GND
I/O
80
I/O
81
I/O
82
I/O
83
I/O
84
I/O
85
I/O
86
I/O
87
GND
I/O
88
I/O
89
I/O
90
I/O
91
I/O
92
I/O
93
I/O
94
I/O
95
I/O
96
I/O
97
I/O
98
I/O
99
I/O
100
I/O
101
I/O
102
I/O
103
GND
GND
CLK
2
/I
3
V
CCIO
CLK
3
/I
4
I/O
104
I/O
105
I/O
106
I/O
107
I/O
108
/SDI
I/O
109
I/O
110
I/O
111
V
CCIO
GND
GND
V
GND
I/O
GND
11
2
CCINT
V
CCIO
V
CCIO
I/O
11
3
I/O
11
4
I/O
11
5
I/O
11
6
I/O
11
7
I/O
11
8
I/O
11
9
I/O
12
0
I/O
12
1
I/O
12
2
I/O
12
3
I/O
12
4
I/O
12
5
I/O
12
6
I/O
12
7
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
ISR
EN
/S
MO
DE
/S
D
O
USE ULTRA37000TM
FOR ALL NEW DESIGNS
CY7C375i
Document #: 38-03029 Rev. *A
Page 3 of 17
Pin Configurations
(continued)
I/O
2
124
3
12
3
4
12
2
5
12
1
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
16
0
45
15
9
46
15
8
47
15
7
48
15
6
49
15
5
50
15
4
51
15
3
52
15
2
53
15
1
54
15
0
55
14
9
56
14
8
57
14
7
58
14
6
59
14
5
60
14
4
61
14
3
62
14
2
63
14
1
64
65
66
67
68
14
0
69
13
9
70
13
8
71
13
7
72
13
6
73
13
5
74
13
4
75
13
3
76
13
2
77
13
1
78
13
0
79
12
9
80
12
8
81
12
7
82
12
6
CQFP
Top View
12
5
84
83
42
1
GND
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
/SCLK
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
GND
CLK
0
/I
0
V
CC
GND
CLK
1
/I
1
GND
GND
48
GND
2
CC
GND
GND
V
CC
I/O
49
I/O
50
I/O
51
I/O
52
I/
O
53
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
I
V
CC
V
64
I/O
65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O
CC
V
GND
I/O
80
I/O
81
I/O
82
I/O
83
I/O
84
I/O
85
I/O
86
I/O
87
GND
I/O
88
I/O
89
I/O
90
I/O
91
I/O
92
I/O
93
I/O
94
I/O
95
I/O
96
I/O
97
I/O
98
I/O
99
I/O
100
I/O
101
I/O
102
I/O
103
GND
GND
CLK
2
/I
3
V
CC
CLK
3
/I
4
I/O
104
I/O
105
I/O
106
I/O
107
I/O
108
/SDI
I/O
109
I/O
110
I/O
111
V
CC
GND
GND
V
GND
I/O
GND
112
CC
V
CC
V
CC
I/O
113
I/O
114
I/O
115
I/O
116
I/O
117
I/O
118
I/O
119
I/O
120
I/O
121
I/O
122
I/O
123
I/O
124
I/O
125
I/O
126
I/O
127
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
ISR
EN
/S
MO
D
E
/SDO
USE ULTRA37000TM
FOR ALL NEW DESIGNS
CY7C375i
Document #: 38-03029 Rev. *A
Page 4 of 17
Functional Description
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource--the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
LASH
370i family, the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 128 I/O pins on the CY7C375i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C375i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
Pin Configurations
(continued)
PGA
Bottom View
1
2
3
4
5
6
7
8
9
10
11
R
P
N
M
L
K
J
H
G
F
E
I/O
109
D
C
B
A
12
13
14
15
I/O
106
I/O
105
I/O
102
I/O
100
I/O
98
I/O
96
I/O
86
I/O
89
I/O
91
I/O
94
I/O
95
I/O
83
I/O
80
I/O
78
I/O
112
I/O
110
I/O
108
I/O
104
I/O
101
I/O
99
I/O
97
I/O
84
I/O
87
I/O
90
I/O
93
GND
I/O
81
I/O
79
I/O
75
/SDI
I/O
115
I/O
113
I/O
111
I/O
107
I/O
103
GND
CLK
3
I/O
82
I/O
85
I/O
88
I/O
92
CLK
2
GND
I/O
77
I/O
74
/I
4
/I
3
I/O
118
I/O
116
I/O
114
V
CC
V
CC
GND
V
CC
GND
I/O
76
I/O
73
I/O
71
/SDO
I/O
121
I/O
119
I/O
117
I/O
72
I/O
70
I/O
69
I/O
123
I/O
122
I/O
120
GND
I/O
68
I/O
67
I/O
126
I/O
125
I/O
124
V
CC
V
CC
I/O
66
I/O
65
I/O
64
I/O
127
GND
ISR
EN
GND
GND
I
2
GND
I/O
63
I/O
0
I/O
1
I/O
2
V
CC
V
CC
I/O
60
I/O
61
I/O
62
I/O
3
I/O
4
GND
I/O
56
I/O
58
I/O
59
I/O
5
I/O
6
I/O
8
I/O
53
I/O
55
I/O
57
I/O
7
I/O
9
I/O
12
GND
V
CC
V
CC
V
CC
GND
I/O
52
/
I/O
50
I/O
71
SMODE
I/O
10
I/O
13
GND
I/O
18
I/O
21
I/O
24
CLK
28
I/O
43
I/O
39
GND
CLK1
CLK
0
I/O
47
I/O
49
I/O
51
/I
0
I/O
11
I/O
15
I/O
17
I/O
20
I/O
23
I/O
26
I/O
29
I/O
40
I/O
37
I/O
35
I/O
33
GND
I/O
44
I/O
46
I/O
48
I/O
14
I/O
16
I/O
19
I/O
22
I/O
25
I/O
27
I/O
30
I/O
38
I/O
36
I/O
34
I/O
32
I/O
31
I/O
41
I/O
42
I/O
45
/I1
/SCLK
USE ULTRA37000TM
FOR ALL NEW DESIGNS
CY7C375i
Document #: 38-03029 Rev. *A
Page 5 of 17
product term sharing help to increase the effective density of
the F
LASH
370i PLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and four global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, "An
Introduction to In System Reprogramming with F
LASH
370i."
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O Operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When V
CCIO
pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all F
LASH
370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device's performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to V
CC
or GND.
Design Tools
Development software for the CY7C375i is available from
Cypress's Warp
, Warp ProfessionalTM, and Warp Enter-
priseTM software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
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