PCIX I/O System Clock Generator with EMI
Control Features
C9530
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07033 Rev. *B
Revised May 9, 2003
Features
Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
Input clock frequency of 25 MHz to 33.3 MHz
Output frequencies of XINx1, XINx2, XINx3 and XINx4
Output grouped in two banks of five clocks each
One REF XIN clock output
SMBus clock control interface for individual clock
disabling and SSCG control and individual back
frequency selection
Output clock duty cycle is 50% ( 5%)
< 250 ps skew between output clocks within a bank
Output jitter < 250 psec (175 psec with all outputs at the
same frequency)
Spread Spectrum feature for reduced electromagnetic
interference (EMI)
OE pins for entire output bank enable control and
testability
48-pin SSOP and TSSOP packages
Note:
1.
A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device's XIN pin. OEA and OEB will three-state
REF.
Table 1. Test Mode Logic Table
[1]
Input Pins
Output Pins
OEA
SA1
SA0
CLKA
REF
OEB
SB1
SB0
CLKB
HIGH
LOW
LOW
XIN
XIN
HIGH
LOW
HIGH
2 * XIN
XIN
HIGH
HIGH
LOW
3 * XIN
XIN
HIGH
HIGH
HIGH
4 * XIN
XIN
LOW
X
X
Three-state
Three-state
Block Diagram
Pin Configuration
XIN
CLKB4
CLKB3
CLKB2
CLKB1
CLKB0
OEB
CLKA3
CLKA2
CLKA1
CLKA0
/N
SSCG#
CLKA4
SSCG
Logic
/N
1
1
0
0
XOUT
I
2
C
Control
Logic
SCLK
OEA
IA(0:2)
AGOOD#
BGOOD#
REF
SDATA
SA(0,1)
SB(0,1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XIN
VDD
XOUT
VSS
SA1
VSS
CLKA0
VDDA
CLKA2
VSS
VDDA
CLKA4
VSS
CLKA1
AGOOD#
VSS
IA1
IA2
AVDD
OEA
OEB
VSS
SSCG#
VSS
AVDD
BGOOD#
AVDD
CLKB4
VDDB
VSS
VDDB
CLKB1
VSS
SB1
VSS
CLKB3
CLKB2
CLKB0
SB0
VDD
VSS
VDD
SCLK
SDATA
IA0
C
953
0
REF
41
42
43
44
45
46
47
48
SA0
CLKA3
C9530
Document #: 38-07033 Rev. *B
Page 2 of 10
Notes:
2.
Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3.
A bypass capacitor (0.1
F) should be placed as close as possible to each V
DD
pin. If these bypass capacitors are not close to the pins their high-frequency
filtering characteristic will be cancelled by the lead inductance of the trace.
4.
PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Pin Description
[3]
Pin
[2]
Name
PWR
[4]
I/O
Description
3
XIN
VDDA
I
Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves
as input clock TCLK, in Test mode.
4
XOUT
VDDA
O
Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used
or in Test mode, this pin is kept unconnected.
1
REF
VDD
O
Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz
24*
OEA
VDD
I
Output Enable for clock bank A. Causes the CLKA output clocks to be in a
three-state condition when driven to a logic low level.
25*
OEB
VDD
I
Output Enable for clock bank B. Causes the CLKB output clocks to be in a
three-state condition when driven to a logic low level.
18
AGOOD#
VDD
O
When this output signal is a logic low level, it indicates that the output clocks of the
A bank are locked to the input reference clock. This output is latched.
31
BGOOD#
VDD
O
When this output signal is at a logic low level, it indicates that the output clocks of
the B bank are locked to the input reference clock. This output is latched.
6*, 7*
SA(0,1)
VDD
I
Clock Bank A selection bits. These control the clock frequency that will be present
on the outputs of the A bank of buffers. SeeTable 1 for frequency codes and selection
values.
43*, 42*
SB(0,1)
VDD
I
Clock Bank B selection bits. These control the clock frequency that will be present
on the outputs of the B bank of buffers. See Table 1 for frequency codes and selection
values.
20*, 21*, 22*
IA(0:2)
VDD
I
SMBus address selection input pins. See Table 3 SMBus Address table.
27*
SSCG#
VDD
I
Enables Spread Spectrum clock modulation when at a logic low level, see Spread
Spectrum Clocking on page 6.
48
SDATA
VDD
I/O Data for the internal SMBus circuitry.
47
SCLK
VDD
I
Clock for the internal SMBus circuitry.
11, 14
VDDA
PW
R
3.3V common power supply pin for Bank A PCI clocks CLKA.
38, 35
VDDB
PW
R
3.3V common power supply pin for Bank B PCI clocks CLKB.
2, 44, 46
VDD
PW
R
Power supply for internal Core logic.
23, 29, 30
AVDD
PW
R
Power for internal analog circuitry. This supply should have a separately
decoupled current source from VDD.
9, 10, 12, 15,
16
CLKA (0:4) VDDA
O
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
40, 39, 37, 34,
33
CLKB (0:4) VDDB
O
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
5, 8, 13, 17,
19, 26, 28, 32,
36, 41, 45
VSS
PWR
Ground pins for the device.
C9530
Document #: 38-07033 Rev. *B
Page 3 of 10
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9530 does not support the Block Read
function.
The block write protocol is outlined in Table 2. The addresses
are listed in Table 3.
Serial Control Registers
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
Description
1
Start
2:8
Slave address 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command Code 8 bits
`00000000' stands for block operation
19
Acknowledge from slave
20:27
Byte Count 8 bits
28
Acknowledge from slave
29:36
Data byte 1 8 bits
37
Acknowledge from slave
38:45
Data byte 2 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N1) 8 bits
....
Acknowledge from slave
....
Data Byte N 8 bits
....
Acknowledge from slave
....
Stop
Table 3. SMBus Address Selection Table
SMBus Address of the Device
IA0 Bit (Pin 10)
IA1 Bit (Pin 11)
IA2 Bit (Pin 12)
DE
0
0
0
DC
1
0
0
DA
0
1
0
D8
1
1
0
D6
0
0
1
D4
1
0
1
D0
0
1
1
D2
1
1
1
Byte 0: Function Select Register
Bit
@Pup
Name
Description
7
1
TESTEN
Test Mode Enable.
1 = Normal operation, 0 = Test mode
6
0
SSEN
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
5
1
SSSEL
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
4
0
S1
SB1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
3
0
S0
SB0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
C9530
Document #: 38-07033 Rev. *B
Page 4 of 10
2
0
SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
1
0
SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
0
1
HWSEL
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 =
SMBus Byte 0 bits 1-4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
Byte0, bit5
Description
0
0
Frequency generated from second PLL
0
1
Frequency generated from XIN
1
0
Spread @ 1.0%
1
1
Spread @ 0.5%
Table 5. Test Table
Test Function Clock
Outputs
CLKA
CLKB
REF
Frequency
XIN/6
XIN/4
XIN
Byte 1: A Bank and REF Clock Control Register
Bit
@Pup
Name
Description
7
1
Reserved
6
1
Reserved
5
1
REFEN
REF Output Enable
0 = Disable, 1= Enable
4
1
CLKA4 Output Enable
0 = Disable, 1= Enable
3
1
CLKA3 Output Enable
0 = Disable, 1= Enable
2
1
CLKA2 Output Enable
0 = Disable, 1= Enable
1
1
CLKA1 Output Enable
0 = Disable, 1= Enable
0
1
CLKA0 Output Enable
0 = Disable, 1= Enable
Byte 2: PCI Register
Bit
@Pup
Name
Description
7
1
Reserved
6
1
Reserved
5
1
Reserved
4
1
18
CLKB4 Output Enable
0 = Disable, 1= Enable
3
1
19
CLKB3 Output Enable
0 = Disable, 1= Enable
2
1
22
CLKB2 Output Enable
0 = Disable, 1= Enable
1
1
23
CLKB1 Output Enable
0 = Disable, 1= Enable
0
1
24
CLKB0 Output Enable
0 = Disable, 1= Enable
Byte 0: Function Select Register (continued)
C9530
Document #: 38-07033 Rev. *B
Page 5 of 10
Internal Crystal Oscillator
This device will operate in two input reference clock configu-
rations. In its simplest mode a 33.33MHz fundamental cut
parallel resonant crystal is attached to the XIN and XOUT pins.
In the second mode a 33.33-MHz input reference clock is
driven in on the IN clock from an external source. In this appli-
cation the XOUT pin must be left disconnected.
Output Clock Three-state Control
All of the clocks in Bank A (CLKA) and Bank B(CLKB) may be
placed in a three-state condition by bringing their relevant OE
pins (OEA and OEB) to a logic low state. This transition to and
from a state and active condition is a totally asynchronous
event and clock glitching may occur during the transitioning
states. This function is intended as a board level testing
feature. When the output clocks are being enabled and
disabled in active environments the SMBus control register
bits are the preferred mechanism to control these signals in an
orderly and predictable manner.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device's S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 Bits 3 and 4 to control
the output clock's frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal
where:
C
XTAL
= The load rating of the crystal.
C
XINFTG
= The clock generators XIN pin effective device internal capacitance to ground.
C
XOUTFTG
= The clock generators XOUT pin effective device internal capacitance to ground.
C
XINPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XOUTPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XINDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
C
XOUTDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
Notes:
5.
For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these
specifications.
6.
Larger values may cause this device to exhibit oscillator startup problems.
Table 6. Suggested Oscillator Crystal Parameters
Parameter
Description
Conditions
Min
Typ.
Max.
Unit
F
o
Frequency
33.0
33.33
33.5
MHz
T
C
Tolerance
See Note 5
100
PPM
T
S
Stability (T
A
10 to +60C) Note 5
100
PPM
T
A
Aging (first year @ 25C) Note 5
5
PPM
Operating Mode
Parallel Resonant, Note 5
C
XTAL
Load Capacitance
The crystal's rated load. Note 5
20
pF
R
ESR
Effective Series Resistance (ESR)
Note 6
40
Ohms
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
) x (C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
) + (C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
C
L
=
PDF 
ZIP