Flash Erasable,

Reprogrammable CMOS PAL

Device

fax id: 6010

PALCE20V8

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

June 1994 Revised March 26, 1997

1P AL CE 20 V8

Features

· Active pull-up on data input pins
· Low power version (20V8L)

-- 55 mA max. commercial (15, 25 ns)

-- 65 mA max. military/industrial

(15, 25 ns)

· Standard version has low power

-- 90 mA max. commercial

(15, 25 ns)

-- 115 mA max. commercial (10 ns)

-- 130 mA max. military/industrial (15, 25 ns)

· CMOS Flash technology for electrical erasability and

reprogrammability

· User-programmable macrocell

-- Output polarity control

-- Individually selectable for registered or combinato-

rial operation

· QSOP package available

-- 10, 15, and 25 ns com'l version

-- 15, and 25 ns military/industrial versions

· High reliability

-- Proven Flash technology

-- 100% programming and functional testing

Functional Description

The Cypress PALCE20V8 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-product (AND-OR) logic struc-
ture and the programmable macrocell.

The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerdip, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and a 24-lead
quarter size outline. The device provides up to 20 inputs and
8 outputs. The PALCE20V8 can be electrically erased and re-
programmed. The programmable macrocell enables the de-
vice to function as a superset to the familiar 24-pin PLDs such
as 20L8, 20R8, 20R6, 20R4.

PAL is a registered trademark of Advanced Micro Devices, Inc.

Logic Block Diagram (PDIP/CDIP/QSOP)

20V81

PROGRAMMABLE

AND ARRAY

(64 x 40)

Macrocell

CLK/I

OE/I

I/O

GND

MUX

PALCE20V8

Shaded area contains preliminary information.

Functional Description

(continued)

The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.

There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.

Power-Up Reset

All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.

Electronic Signature

An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.

Security Bit

A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.

Low Power

The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.

Product Term Disable

Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.

Input and I/O Pin Pull-Ups

The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, V

, or

Ground to improve noise immunity and reduce I

Pin Configuration

PLCC/LCC

Top View

20V82

DIP/QSOP

Top View

25
24
23
22
21
20
19

5
6
7
8
9
10
11

121314 1516 1718

4 3 2

2827 26

1
2
3
4

5
6

7
8
9
10
11

20
19
18
17

24
23
22

OE/I

I/O

GND

CLK/I

20V83

I/O

Selection Guide

Generic Part Number

Com'l/Ind

Mil

Com'l/Ind

Mil

Com'l/Ind

Mil

Com'l

Mil/Ind

PALCE20V8

115

PALCE20V8

7.5

115

PALCE20V8

115

130

PALCE20V8

130

PALCE20V8

130

PALCE20V8L

PALCE20V8

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature

..................................... -

C to +150

Ambient Temperature with
Power Applied

.................................................. -

C to +125

Supply Voltage to Ground Potential
(Pin 24 to Pin 12)

.................................................-

0.5V to +7.0V

DC Voltage Applied to Outputs
in High Z State

.....................................................-

0.5V to +7.0V

DC Input Voltage

.................................................-

0.5V to +7.0V

Output Current into Outputs (LOW)............................. 24 mA

DC Programming Voltage............................................. 12.5V

Latch-Up Current ..................................................... >200 mA

Configuration Table

CL0

Cell Configuration

Devices Emulated

Registered Output

Registered Med PALs

Combinatorial I/O

Registered Med PALs

Combinatorial Output

Small PALs

Input

Small PALs

Combinatorial I/O

20L8 only

Macrocell

CLK

20V84

CL1

1 1

I/O

From
Adjacent
Pin

CL0

for pin 16 to 21 (DIP)

for pin 15 and 22 (DIP)

1 1

0 0

1 1

Adjacent

Macrocell

CL0

Operating Range

Range

Ambient

Temperature

Commercial

C to +75

Industrial

C to +85

10%

Military

[1]

C to +125

10%

Note:

is the "instant on" case temperature.

PALCE20V8

Electrical Characteristics

Over the Operating Range

[2]

Parameter

Description

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min.,

= V

or V

3.2 mA

Com'l

2.4

2 mA

Mil/Ind

Output LOW Voltage

= Min.,

= V

or V

= 24 mA

Com'l

0.5

= 12 mA

Mil/Ind

Input HIGH Level

Guaranteed Input Logical HIGH Voltage for All Inputs

[3]

2.0

[4]

Input LOW Level

Guaranteed Input Logical LOW Voltage for All Inputs

[3]

0.5

0.8

Input or I/O HIGH Leakage
Current

3.5V < V

< V

[5]

Input or I/O LOW Leakage
Current

0V < V

< V

(Max.)

100

Output Short Circuit Current V

= Max., V

OUT

= 0.5V

[6,7]

150

Operating Power Supply
Current

= Max.,

= 0V, V

= 3V,

Output Open,
f = 15 MHz
(counter)

5, 7, 10 ns

Com'l

115

15, 25 ns

15L, 25L ns

10, 15, 25 ns

Mil/Ind

130

15L, 25L ns

Mil/Ind

Capacitance

[7]

Parameter

Description

Test Conditions

Typ.

Unit

Input Capacitance

= 2.0V @ f = 1 MHz

OUT

Output Capacitance

OUT

= 2.0V @ f = 1 MHz

Endurance Characteristics

[7]

Parameter

Description

Test Conditions

Min.

Max.

Unit

Minimum Reprogramming Cycles

Normal Programming Conditions

100

Cycles

Notes:

See the last page of this specification for Group A subgroup testing information.

These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

(Min.) is equal to

3.0V for pulse durations less than 20 ns.

The leakage current is due to the internal pull-up resistor on all pins.

Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V

OUT

= 0.5V has been chosen to avoid test problems

caused by tester ground degradation.

Tested initially and after any design or process changes that may affect these parameters.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PAL20V8

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PAL20V8