Flash Erasable,
Reprogrammable CMOS PAL Device
PALCE22V10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03027 Rev. **
Revised September 1996
22V10
Features
Low power
-- 90 mA max. commercial (10 ns)
-- 130 mA max. commercial (5 ns)
CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
Variable product terms
-- 2 x(8 through 16) product terms
User-programmable macrocell
-- Output polarity control
-- Individually selectable for registered or combinato-
rial operation
Up to 22 input terms and 10 outputs
DIP, LCC, and PLCC available
-- 5 ns commercial version
4 ns t
CO
3 ns t
S
5 ns t
PD
181-MHz state machine
-- 10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-MHz state machine
-- 15-ns commercial, industrial, and military versions
-- 25-ns commercial, industrial, and military versions
High reliability
-- Proven Flash EPROM technology
-- 100% programming and functional testing
Functional Description
The Cypress PALCE22V10 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
PAL is a registered trademark of Advanced Micro Devices.
Logic Block Diagram (PDIP/CDIP)
Pin Configuration
CE22V101
PLCC
Top View
Macrocell
8
10
12
14
16
16
14
12
10
8
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
Preset
PROGRAMMABLE
AND ARRAY
(132 X 44)
I
I
I
I
I
I
I
I
I
I
CP/I
VSS
I
I/O9
I/O8
I/O 7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP/I
V
I/O
I/O
8
I/O
I/O
I
V
I
I
SS
0
1
CC
N/C
LCC
Top View
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP/I
V
I/O
I/O
8
I/O
I/O
I
V
I
I
SS
0
1
CC
1
N/C
NC
NC
NC
NC
NC
NC
CE22V102
CE22V103
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
1
PALCE22V10
Document #: 38-03027 Rev. **
Page 2 of 13
Functional Description
(continued)
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as "registered" or "combinatorial." Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through "array" configurable "output enable" for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Selection Guide
Generic Part Number
t
PD
ns
t
S
ns
t
CO
ns
I
CC
mA
Com'l
Mil/Ind
Com'l
Mil/Ind
Com'l
Mil/Ind
Com'l
Mil/Ind
PALCE22V10-5
5
3
4
130
PALCE22V10-7
7.5
5
5
130
PALCE22V10-10
10
10
6
6
7
7
90
150
PALCE22V10-15
15
15
10
10
8
8
90
120
PALCE22V10-25
25
25
15
15
15
15
90
120
Configuration Table
Registered/Combinatorial
C
1
C
0
Configuration
0
0
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
PALCE22V10
Document #: 38-03027 Rev. **
Page 3 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150
C
Ambient Temperature with
Power Applied.............................................55
C to +125
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
DC Programming Voltage............................................. 12.5V
Latch-Up Current ..................................................... >200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2001V
Note:
1.
T
A
is the "instant on" case temperature.
Macrocell
OUTPUT
SELECT
MUX
AR
S
S
1
0
Q
Q
D
CP
SP
INPUT/
FEEDBACK
MUX
1
S
MACROCELL
1
C
0
C
CE22V104
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +75
C
5V
5%
Industrial
40
C to +85
C
5V
10%
Military
[1]
55
C to +125
C
5V
10%
PALCE22V10
Document #: 38-03027 Rev. **
Page 4 of 13
]
]
Electrical Characteristics
Over the Operating Range
[2]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OH
= 3.2 mA
Com'l
2.4
V
I
OH
= 2 mA
Mil/Ind
V
OL
Output LOW Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OL
= 16 mA
Com'l
0.5
V
I
OL
= 12 mA
Mil/Ind
V
IH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
[3]
2.0
V
V
IL
[4]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
[3]
0.5
0.8
V
I
IX
Input Leakage Current
V
SS
< V
IN
< V
CC
, V
CC
= Max.
10
10
A
I
OZ
Output Leakage Current
V
CC
= Max., V
SS
< V
OUT
< V
CC
40
40
A
I
SC
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[5,6]
30
130
mA
I
CC1
Standby Power Supply
Current
V
CC
= Max.,
V
IN
= GND,
Outputs Open in
Unprogrammed
Device
10, 15, 25 ns
Com'l
90
mA
5, 7.5 ns
130
mA
15, 25 ns
Mil/Ind
120
mA
10 ns
120
mA
I
CC2
[6]
Operating Power Supply
Current
V
CC
= Max., V
IL
=
0V, V
IH
= 3V,
Output Open, De-
vice Programmed
as a 10-Bit
Counter,
f = 25 MHz
10, 15, 25 ns
Com'l
110
mA
5, 7.5 ns
Com'l
140
mA
15, 25 ns
Mil/Ind
130
mA
10 ns
Mil/Ind
130
mA
Capacitance
[6]
Parameter
Description
Test Conditions
Min.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 2.0V @ f = 1 MHz
10
pF
C
OUT
Output Capacitance
V
OUT
= 2.0V @ f = 1 MHz
10
pF
Endurance Characteristics
[6]
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions
100
Cycles
Notes:
2.
See the last page of this specification for Group A subgroup testing information.
3.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4.
V
IL
(Min.) is equal to -3.0V for pulse durations less than 20 ns.
5.
Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6.
Tested initially and after any design or process changes that may affect these parameters.
PALCE22V10
Document #: 38-03027 Rev. **
Page 5 of 13
AC Test Loads and Waveforms
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
C
L
(a)
(b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(c)
OUTPUT
C
L
R1238
(319
MIL)
R1238
(319
MIL)
R2170
(236
MIL)
R2170
(236
MIL)
750
(1.2K
MIL)
OUTPUT
2.08V=V
thc
OUTPUT
2.13V=V
thm
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
< 2 ns
< 2 ns
(d)
99
136
Equivalent to:
TH VENIN EQUIVALENT (Commercial)
Equivalent to:
TH VENIN EQUIVALENT (Military)
CE22V105
CE22V106
CE22V107
Load Speed
C
L
Package
5, 7.5, 10, 15, 25
ns
50 pF
PDIP, CDIP,
PLCC, LCC
Parameter
V
X
Output Waveform Measurement Level
t
ER (- )
1.5V
V
OH
0.5V
V
X
0.5V
t
ER (+)
2.6V
V
OL
V
X
t
EA (+)
0V
0.5V
t
EA (- )
V
thc
V
X
V
OL
1.5V
V
X
V
OH
(e) Test Waveforms
PALCE22V10
Document #: 38-03027 Rev. **
Page 6 of 13
]
Commercial Switching Characteristics PALCE22V10
[2,7]
Description
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PD
Input to Output
Propagation Delay
[8]
3
5
3
7.5
3
10
3
15
3
25
ns
t
EA
Input to Output
Enable Delay
[9]
6
8
10
15
25
ns
t
ER
Input to Output
Disable Delay
[10]
6
8
10
15
25
ns
t
CO
Clock to Output Delay
[8]
2
4
2
5
2
7
2
8
2
15
ns
t
S1
Input or Feedback Set-Up Time
3
5
6
10
15
ns
t
S2
Synchronous Preset Set-Up
Time
4
6
7
10
15
ns
t
H
Input Hold Time
0
0
0
0
0
ns
t
P
External Clock Period (t
CO
+ t
S
)
7
10
12
20
30
ns
t
WH
Clock Width HIGH
[6]
2.5
3
3
6
13
ns
t
WL
Clock Width LOW
[6]
2.5
3
3
6
13
ns
f
MAX1
External Maximum
Frequency (1/(t
CO
+ t
S
))
[11]
143
100
76.9
55.5
33.3
MHz
f
MAX2
Data Path Maximum Frequency
(1/(t
WH
+ t
WL
))
[6, 12]
200
166
142
83.3
35.7
MHz
f
MAX3
Internal Feedback Maximum
Frequency (1/(t
CF
+ t
S
))
[6,13]
181
133
111
68.9
38.5
MHz
t
CF
Register Clock to
Feedback Input
[6,14]
2.5
2.5
3
4.5
13
ns
t
AW
Asynchronous Reset Width
8
8
10
15
25
ns
t
AR
Asynchronous Reset
Recovery Time
4
5
6
10
25
ns
t
AP
Asynchronous Reset to
Registered Output Delay
7.5
12
13
20
25
ns
t
SPR
Synchronous Preset
Recovery Time
4
6
8
10
15
ns
t
PR
Power-Up Reset Time
[6,15]
1
1
1
1
1
s
Notes:
7.
Part (a) of AC Test Loads and Waveforms is used for all parameters except t
ER
and t
EA(+)
. Part (b) of AC Test Loads and Waveforms is used for t
ER
. Part (c) of AC Test
Loads and Waveforms is used for t
EA(+)
.
8.
Min. times are tested initially and after any design or process changes that may affect these parameters.
9.
The test load of part (a) of AC Test Loads and Waveforms is used for measuring t
EA(-)
. The test load of part (c) of AC Test Loads and Waveforms is used for measuring
t
EA(+)
only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below V
OH
min. or a previous LOW level has risen to 0.5 volts above V
OL
max. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
11.
This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f
MAX
internal (1/f
MAX3
) as measured (see Note above) minus t
S
.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in V
CC
must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied
PALCE22V10
Document #: 38-03027 Rev. **
Page 7 of 13
Military and Industrial Switching Characteristics PALCE22V10
[2,7]
22V10-10
22V10-15
22V10-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
PD
Input to Output
Propagation Delay
[8]
3
10
3
15
3
25
ns
t
EA
Input to Output Enable Delay
[9]
10
15
25
ns
t
ER
Input to Output Disable Delay
[10]
10
15
25
ns
t
CO
Clock to Output Delay
[8]
2
7
2
8
2
15
ns
t
S1
Input or Feedback Set-Up Time
6
10
18
ns
t
S2
Synchronous Preset Set-Up
Time
7
10
18
ns
t
H
Input Hold Time
0
0
0
ns
t
P
External Clock Period (t
CO
+ t
S
)
12
20
33
ns
t
WH
Clock Width HIGH
[6]
3
6
14
ns
t
WL
Clock Width LOW
[6]
3
6
14
ns
f
MAX1
External Maximum Frequency
(1/(t
CO
+ t
S
))
11]
76.9
50.0
30.3
MHz
f
MAX2
Data Path Maximum Frequency
(1/(t
WH
+ t
WL
))
[6,12 ]
142
83.3
35.7
MHz
f
MAX3
Internal Feedback Maximum
Frequency (1/(t
CF
+ t
S
))
[6,13]
111
68.9
32.2
MHz
t
CF
Register Clock to
Feedback Input
[6,14]
3
4.5
13
ns
t
AW
Asynchronous Reset Width
10
15
25
ns
t
AR
Asynchronous Reset
Recovery Time
6
12
25
ns
t
AP
Asynchronous Reset to
Registered Output Delay
12
20
25
ns
t
SPR
Synchronous Preset
Recovery Time
8
20
25
ns
t
PR
Power-Up Reset Time
[6,15]
1
1
1
s
PALCE22V10
Document #: 38-03027 Rev. **
Page 8 of 13
Switching Waveforms
t
S
t
H
t
WL
t
WH
t
P
t
SPR
t
AR
t
AW
t
AP
t
CO
t
PD
t
ER
t
EA
t
ER
t
EA
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
CP
ASYNCHRONOUS
RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
CE22V108
[10]
[10]
[9]
[9]
Power-Up Reset Waveform
[15]
t
PR
POWER
CLOCK
t
S
t
WL
10%
REGISTERED
ACTIVE LOW
OUTPUTS
SUPPLY VOLTAGE
t
PR
MAX = 1
s
90%
V
CC
CE22V109
PALCE22V10
Document #: 38-03027 Rev. **
Page 9 of 13
Functional Logic Diagram for PALCE22V10
0
1
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
Macro
cell
2
3
4
5
6
7
8
9
10
11
23
22
21
20
19
18
17
16
15
14
13
16
20
24
28
32
36
40
AR
OE
0
7
OE
0
9
OE
0
11
OE
0
13
OE
0
15
OE
0
15
OE
0
13
OE
0
11
OE
0
9
OE
0
7
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
SP
12
8
4
CE22V1010
PALCE22V10
Document #: 38-03027 Rev. **
Page 10 of 13
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
I
CC
(mA)
t
PD
(ns)
t
S
(ns)
t
CO
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
130
5
3
4
PALCE22V10-5PC
P13
24-Lead (300 MIL) Molded DIP
Commercial
PALCE22V10-5JC
J64
28-Lead Plastic Leaded Chip Carrier
130
7.5
5
5
PALCE22V10-7JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
PALCE22V10-7PC
P13
24-Lead (300-Mil) Molded DIP
90
10
6
7
PALCE22V10-10JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
PALCE22V10-10PC
P13
24-Lead (300-Mil) Molded DIP
150
10
6
7
PALCE22V10-10JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
PALCE22V10-10PI
P13
24-Lead (300-Mil) Molded DIP
150
10
6
7
PALCE22V10-10DMB
D14
24-Lead (300-Mil) CerDIP
Military
PALCE22V10-10KMB
K73
24-Lead Rectangular Cerpack
PALCE22V10-10LMB
L64
28-Square Leadless Chip Carrier
90
15
7.5
10
PALCE22V10-15JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
PALCE22V10-15PC
P13
24-Lead (300-Mil) Molded DIP
120
15
7.5
10
PALCE22V10-15JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
PALCE22V10-15PI
P13
24-Lead (300-Mil) Molded DIP
120
15
7.5
10
PALCE22V10-15DMB
D14
24-Lead (300-Mil) CerDIP
Military
PALCE22V10-15KMB
K73
24-Lead Rectangular Cerpack
PALCE22V10-15LMB
L64
28-Square Leadless Chip Carrier
90
25
15
15
PALCE22V10-25JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
PALCE22V10-25PC
P13
24-Lead (300-Mil) Molded DIP
120
25
15
15
PALCE22V10-25JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
PALCE22V10-25PI
P13
24-Lead (300-Mil) Molded DIP
120
25
15
15
PALCE22V10-25DMB
D14
24-Lead (300-Mil) CerDIP
Military
PALCE22V10-25KMB
K73
24-Lead Rectangular Cerpack
PALCE22V10-25LMB
L64
28-Square Leadless Chip Carrier
DC Characteristics
Parameter
Subgroups
V
OH
1, 2, 3
V
OL
1, 2, 3
V
IH
1, 2, 3
V
IL
1, 2, 3
I
IX
1, 2, 3
I
OZ
1, 2, 3
I
CC
1, 2, 3
Switching Characteristics
Parameter
Subgroups
t
PD
9, 10, 11
t
CO
9, 10, 11
t
S
9, 10, 11
t
H
9, 10, 11
PALCE22V10
Document #: 38-03027 Rev. **
Page 11 of 13
Package Diagrams
24Lead (300Mil) CerDIP D14
MIL-STD-1835
D- 9 Config.A
28Lead Plastic Leaded Chip Carrier J64
24Lead Rectangular Cerpack K73
MIL-STD-1835
F- 6 Config.A
28Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
PALCE22V10
Document #: 38-03027 Rev. **
Page 12 of 13
Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
24Lead (300Mil) Molded DIP P13/P13A
PALCE22V10
Document #: 38-03027 Rev. **
Page 13 of 13
Document Title: PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL Device
Document Number: 38-03027
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106372
07/11/01
SZV
Change from Spec Number: 38-00447 to 38-03027
PDF 
ZIP