440BX AGPset Spread Spectrum Frequency Synthesizer
W149
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07176 Rev. *A
Revised December 22, 2002
Features
Maximized EMI suppression using Cypress's Spread
Spectrum Technology
Single chip system frequency synthesizer for Intel
440BX AGPset
Two copies of CPU output
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz output for SIO
Two buffered reference outputs
One IOAPIC output
Thirteen SDRAM outputs provide support for 3 DIMMs
Spread Spectrum feature always enabled
SMBus interface for programming
Power management control inputs
Smooth CPU frequency switching from 66.8124 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: ..................................................................... 3.3V5%
V
DDQ2
: ..................................................................... 2.5V5%
SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ.
Table 1. Mode Input Table
[1]
Mode
Pin 2
0
PCI_STOP#
1
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU0:1
(MHz)
PCI_F, 1:5
(MHz)
Spread%
FS2
FS1
FS0
1
1
1
100
33.3 (CPU/3)
0.5
1
1
0
(Reserved)
1
0
1
100
33.3 (CPU/3)
0.5
1
0
0
103
34.3 (CPU/3)
0.5
0
1
1
66.8
33.4 (CPU/2)
0.5
0
1
0
83.3
41.7 (CPU/2)
0.5
0
0
1
66.8
33.4 (CPU/2)
0.5
0
0
0
124
41.3 (CPU/3)
0.5
Intel is a registered trademark of Intel Corporation.
Notes:
1.
Mode input latched at power-up.
2.
Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Logic Block Diagram
Pin Configuration
[2]
VDDQ3
REF0/(PCI_STOP#)
VDDQ2
CPU0
PCI_F/MODE
XTAL
PLL Ref Freq
PLL 1
X2
X1
REF1/FS2
VDDQ3
Stop
Clock
Control
PCI2
PCI3
PCI4
48MHz/FS0
24MHz/FS1
PLL2
2/3
OSC
VDDQ2
VDDQ3
IOAPIC
PCI5
SMBus
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:12
SDRAMIN
13
VDDQ3
PCI1
CPU1
2
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDATA
SCLK
W14
9
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU0
CPU1
VDDQ2
OE
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SMBus
{
W149
Document #: 38-07176 Rev. *A
Page 2 of 16
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPU0:1
44, 43
O
CPU Clock Outputs: See Tables 2 and 6 for detailed frequency information. Output
voltage swing is controlled by voltage applied to VDDQ2.
PCI1:5
8, 10, 11, 12,
13
O
PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by
the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F/MODE
7
I/O
Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial
input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP#
input. Upon power-up the mode input will be latched, which will determine the func-
tion of pin 2, REF0/(PCI_STOP#). See Table 1.
OE
41
I
Output Enable Input: When brought LOW, all outputs are placed in a high-imped-
ance state. When brought HIGH, all clock outputs activate.
IOAPIC
47
O
IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48MHz/FS0
26
I/O
48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this
output can be used as the reference for the Universal Serial Bus. Upon power-up,
FS0 input will be latched, which will set clock frequencies as described in Table 2.
This output does not have the Spread Spectrum feature.
24MHz/FS1
25
I/O
24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this
output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input
will be latched, which will set clock frequencies as described in Table 2. This output
does not have the Spread Spectrum feature.
REF1/FS2
46
I/O
I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched
which will set clock frequencies as described in Table 2. When an output, this pin
provides a fixed clock signal equal in frequency to the reference signal provided at
the X1/X2 pins.
REF0/
(PCI_STOP#)
2
I/O
Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the
MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5
outputs when HIGH and causes them to remain at logic 0 when LOW. The
PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on
the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal
equal in frequency to the reference signal provided at the X1/X2 pins.
SDRAMIN
15
I
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
SDRAM0:12
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17, 40
O
Buffered Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deacti-
vated when CLK_STOP# input is set LOW.
SCLK
24
I
Clock pin for SMBus circuitry.
SDATA
23
I/O
Data pin for SMBus circuitry.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19,
27, 30, 36
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to
3.3V supply.
VDDQ2
42, 48
P
Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect
to 2.5V, or 3.3V.
GND
3, 9, 16, 22,
33, 39, 45
G
Ground Connections: Connect all ground pins to the common system ground
plane.
W149
Document #: 38-07176 Rev. *A
Page 3 of 16
Overview
The W149 was developed as a single chip device to meet the
clocking needs of the Intel 440BX AGPset. In addition to the
typical outputs provided by standard 100-MHz 440BX AGPset
FTGs, the W149 adds a thirteen output buffer, supporting
SDRAM DIMM modules in conjunction with the chipset.
Cypress proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. This fea-
ture reduces the peak EMI measurements of not only the out-
put signals and their harmonics, but also of any other clock
signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 25, 26, 46 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to "0", connection to V
DD
sets a latch to "1". Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W149 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the four I/O pins (7,
25, 26, 46) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull each pin and its associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
of the 2-ms period, the established logic "0" or "1" condition of
the l/O pin is latched. Next the output buffer is enabled, con-
verting the l/O pins into operating clock outputs. The 2-ms tim-
er starts when V
DD
reaches 2.0V. The input bits can only be
reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output is <40
(nominal), which is minimally
affected by the 10-k
strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W149
V
DD
Clock Load
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W149
V
DD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
W149
Document #: 38-07176 Rev. *A
Page 4 of 16
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is either 0.5% or 0.5% of the
selected frequency. Figure 4 details the Cypress spreading
pattern. Cypress does offer options with more spread and
greater EMI reduction. Contact your local Sales representative
for details on these devices.
Spread Spectrum clocking cannot be deactivated on the
W149.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
SSFTG
Typical Clock
Frequency Span (MHz)
Am
p
l
i
t
u
d
e
(
d
B
)
Center Spread
MAX (+0.5%)
MIN (0.5%)
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
100
%
FREQUENC
Y
Figure 4. Typical Modulation Profile
W149
Document #: 38-07176 Rev. *A
Page 5 of 16
Serial Data Interface
The W149 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W149 initializes
with default register settings, therefore the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W149 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Output Three-state
Puts clock output into a high-impedance state.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W149 to accept the bits in Data Bytes 06 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W149 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command Code
Don't Care
Unused by the W149, therefore bit values are ignored ("Don't Care").
This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
3
Byte Count
Don't Care
Unused by the W149, therefore bit values are ignored ("Don't Care").
This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 5
The data bits in Data Bytes 07 set internal W149 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
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