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Электронный компонент: W158H

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Spread Spectrum System Frequency Synthesizer
W158
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07164 Rev. *A
Revised December 14, 2002
Features
Maximized EMI suppression using Cypress's spread
spectrum technology
Intel CK98 Specification compliant
0.5% downspread outputs deliver up to 10 dB lower EMI
Four skew-controlled copies of CPU output
Eight copies of PCI output (synchronous w/CPU output)
Four copies of 66-MHz fixed frequency 3.3V clock
Two copies of CPU/2 outputs for synchronous memory
reference
Three copies of 16.67-MHz IOAPIC clock, synchronous
to CPU clock
One copy of 48-MHz USB output
Two copies of 14.31818-MHz reference clock
Programmable to 133- or 100-MHz operation
Power management control pins for clock stop and shut
down
Available in 56-pin SSOP
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V5%
V
DDQ2
= 2.5V5%
CPU Output Jitter: ...................................................... 150 ps
CPUdiv2, IOAPIC Output Jitter: .................................. 250 ps
48 MHz, 3V66, PCI Output Jitter: ................................ 500 ps
CPU0:3, CPUdiv2_ 0:1 Output Skew: ......................... 175 ps
PCI_F, PCI1:7 Output Skew: ....................................... 500 ps
3V66_0:3, IOAPIC0:2 Output Skew: ........................... 250 ps
CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-k
pull-up
resistors
Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Frequency
[1]
SEL133/100#
CPU0:3 (MHz)
PCI
1
133 MHz
33.3 MHz
0
100 MHz
33.3 MHz
Note:
1.
See Table 2 for complete mode selection details.
Block Diagram
Pin Configuration
REF0:1
CPU0:3
CPUdiv2_0:1
3V66_0:3
XTAL
PLL 1
SPREAD#
X2
X1
PCI_F
PCI1:7
IOAPIC0:2
48MHz
PLL2
OSC
2
STOP
Logic
Power
Three-state
Logic
SEL0
SEL1
SEL133/100#
Clock
CPU_STOP#
2/1.5
STOP
Logic
Clock
Down
Logic
2
STOP
Logic
Clock
2
2
4
2
4
1
7
3
1
PCI_STOP#
PWRDWN#
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
W1
5
8
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
VDDQ2
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
3V66_2
3V66_3
VDDQ3
SEL133/100#
SEL0
VDDQ3
48MHz
GND
W158
Document #: 38-07164 Rev. *A
Page 2 of 13
Overview
The W158 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel architec-
ture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W158 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also
provides skew-controlled PCI and IOAPIC clocks synchro-
nous to CPU clock, 48-MHz Universal Serial Bus (USB) clock,
and replicates the 14.31818-MHz reference clock.
All CPU, PCI, and IOAPIC clocks can be synchronously mod-
ulated for spread spectrum operations. Cypress employs pro-
prietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. Spread Spectrum modulation is enabled by
the active LOW control signal SPREAD#.
The W158 also includes power management control inputs.
By using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU0:3
41, 42, 45, 46
O
CPU Clock Outputs 0 through 3: These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1
49, 50
O
Synchronous Memory Reference Clock Output 0 through 1: Reference clock for Di-
rect RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage swing
is set by the voltage applied to VDDQ2.
PCI1:7
9, 11, 12, 14,
15, 17, 18
O
PCI Clock Outputs 1 through 7: These seven PCI clock outputs run synchronously to
the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs
are stopped when PCI _STOP# is held LOW.
PCI_F
8
O
PCI_F (PCI Free-running): This PCI clock output runs synchronously to the CPU clock.
Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the state
of PCI_STOP#.
REF0:1
2, 3
O
14.318-MHz Reference Clock Output: 3.3V copies of the 14.318-MHz reference clock.
IOAPIC0:2
53, 54, 55
O
I/O APIC Clock Output: Provides 16.67-MHz fixed frequency. The output voltage swing
is set by the power connection to VDDQ2.
48MHz
30
O
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:3
21, 22, 25, 26
O
66-MHz Output 0 through 3: Fixed 66-MHz outputs. Output voltage swing is controlled
by voltage applied to VDDQ3.
SEL0:1
32, 33
I
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output
modes.
SEL133/100#
28
I
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output fre-
quency as shown in Table 1.
X1
5
I
Crystal Connection or External Reference Frequency Input: Connect to either a
14.318-MHz crystal or an external reference signal.
X2
6
O
Crystal Connection: An output connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
SPREAD#
34
I
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
PWRDWN#
35
I
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that re-
quests the device to enter power-down mode.
CPU_STOP#
36
I
Active LOW CPU Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input.
PCI_STOP#
37
I
Active LOW PCI Clock Stop: 3.3V LVTTL-compatible asynchronous input that stops all
PCI outputs except PCI_F when held LOW.
VDDQ3
4, 10, 16, 23,
27, 31, 39
P
Power Connection: Power supply for PCI output buffers, 48-MHz USB output buffer,
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to
3.3V supply.
VDDQ2
43, 47, 51, 56
P
Power Connection: Power supply for IOAPIC, CPU, and CPUdiv2 output buffers. Con-
nect to 2.5V supply.
GND
1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
G
Ground Connection: Connect all ground pins to the common system ground plane.
W158
Document #: 38-07164 Rev. *A
Page 3 of 13
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
As shown in Figure 1, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5% downspread. Figure
2
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
60%
20%
80%
40%
0%
20%
40%
60%
80%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Time
Frequen
cy S
h
i
f
t
Figure 2. Modulation Waveform Profile
W158
Document #: 38-07164 Rev. *A
Page 4 of 13
Mode Selection Functions
The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Notes:
2.
Provided for board level "bed of nails" testing.
3.
48-MHz PLL disabled to reduce component jitter.
4.
Normal" mode of operation.
5.
TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6.
Required for DC output impedance verification.
7.
Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8.
Frequency accuracy of 48 MHz is +167 PPM to match USB default.
Table 2. Select Functions
SEL133/100#
SEL1
SEL0
Function
0
0
0
All Outputs Three-State
0
0
1
(Reserved)
0
1
0
Active 100-MHz, 48-MHz PLL Inactive
0
1
1
Active 100-MHz, 48-MHz PLL Active
1
0
0
Test Mode
1
0
1
(Reserved)
1
1
0
Active 133-MHz, 48-MHz PLL Inactive
1
1
1
Active 133-MHz, 48-MHz PLL Active
Table 3. Truth Table
SEL
133/100#
SEL1
SEL0
CPU
CPUdiv2
3V66
PCI
48MHz
REF
IOAPIC
Notes
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
2
0
0
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0
1
0
100 MHz
50 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz 16.67 MHz
3
0
1
1
100 MHz
50 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz 16.67 MHz
4, 7, 8
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK16
5, 6
1
0
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
1
0
133 MHz
66 MHz
66 MHz
33 MHz
HI-Z
14.318 MHz 16.67 MHz
3
1
1
1
133 MHz
66 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz 16.67 MHz
4, 7, 8
Table 4. Maximum Supply Current
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
=2.625V
All static inputs=V
DDQ3
or GND
Max. 3.3V supply consumption
Max. discrete cap loads,
V
DDQ3
=3.465V or GND
Powerdown Mode
(PWRDWN#=0)
100 A
200 A
Full Active 100 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
75 mA
160 mA
Full Active 133 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
90 mA
160 mA
W158
Document #: 38-07164 Rev. *A
Page 5 of 13
Table 5. Clock Enable Configuration
[9, 10, 11, 12, 13, 14]
CPU_STOP# PWRDWN# PCI_STOP#
CPU
CPUdiv2
IOAPIC
3V66
PCI
PCI_F
REF,
48MHz
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
Table 6. Power Management State Transition
[15, 16]
Signal
Signal State
Latency
No. of rising edges of PCI Clock
CPU_STOP#
0 (disabled)
1
1 (enabled)
1
PCI_STOP#
0 (disabled)
1
1 (enabled)
1
PWRDWN#
1 (normal operation)
3 ms
0 (power down)
2 max.
Timing Diagrams
CPU_STOP# Timing Diagram
[17, 18, 19, 20, 21, 22]
Notes:
9.
LOW means outputs held static LOW as per latency requirement below.
10. ON means active.
11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
14. An "x" indicates a "don't care" condition.
15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first
valid clock comes out of the device.
16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
17. All internal timing is referenced to the CPU clock.
18. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
20. 3V66 clocks also stop/start before.
21. PWRDWN# and PCI_STOP# are shown in a HIGH state.
22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
CPU
PCI
CPU_STOP#
PCI_STOP#
PWRDWN#
3V66
(internal)
HI
HI
CPU
(external)
W158
Document #: 38-07164 Rev. *A
Page 6 of 13
PCI_STOP# Timing Diagram
[18, 22, 23, 24, 25, 26]
PWRDWN# Timing Diagram
[18, 22, 23, 27, 28]
Notes:
23. All internal timing is referenced to the CPU clock.
24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.
25. All other clocks continue to run undisturbed.
26. PWRDWN# and CPU_STOP# are shown in a HIGH state.
27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized.
28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.
Timing Diagrams
(continued)
CPU
PCI
PCI_STOP#
PWRDWN#
PCI_F
(external)
HI
HI
(internal)
PCI
(external)
CPU_STOP#
CPU
PCI
PWRDWN#
VCO
Crystal
PCI
CPU
(internal)
(internal)
(external)
(external)
W158
Document #: 38-07164 Rev. *A
Page 7 of 13
Absolute Maximum Ratings
[29]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
ESD
PROT
Input ESD Protection
2 (min.)
kV
DC Electrical Characteristics:
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
DD-3.3V
Combined 3.3V Supply Current
CPU0:3 =133 MHz
[30]
160
mA
I
DD-2.5
Combined 2.5V Supply Current
CPU0:3 =133 MHz
[30]
90
mA
Logic Inputs (All referenced to V
DDQ3
= 3.3V)
V
IL
Input Low Voltage
GND
0.3
0.8
V
V
IH
Input High Voltage
2.0
VDD+
0.3
V
I
IL
Input Low Current
[31]
25
A
I
IH
Input High Current
[31]
10
A
I
IL
Input Low Current, SEL133/100#
[31]
5
A
I
IH
Input High Current, SEL133/100#
[31]
5
A
Clock Outputs
CPU, CPUdiv2, IOAPIC (Referenced to V
DDQ2
)
Test Condition
Min.
Typ.
Max.
Unit
V
OL
Output Low Voltage
I
OL
= 1 mA
50
mV
V
OH
Output High Voltage
I
OH
= 1 mA
2.2
V
I
OL
Output Low Current
V
OL
= 1.25V
45
65
100
mA
I
OH
Output High Current
V
OH
= 1.25V
45
65
100
mA
48MHz, REF (Referenced to V
DDQ3
)
Test Condition
Min.
Typ.
Max.
Unit
V
OL
Output Low Voltage
I
OL
= 1 mA
50
mV
V
OH
Output High Voltage
I
OH
= 1 mA
3.1
V
I
OL
Output Low Current
V
OL
= 1.5V
45
65
100
mA
I
OH
Output High Current
V
OH
= 1.5V
45
65
100
mA
PCI, 3V66 (Referenced to V
DDQ3
)
Test Condition
Min.
Typ.
Max.
Unit
V
OL
Output Low Voltage
I
OL
= 1 mA
50
mV
V
OH
Output High Voltage
I
OH
= 1 mA
3.1
V
I
OL
Output Low Current
V
OL
= 1.5V
70
100
145
mA
I
OH
Output High Current
V
OH
= 1.5V
65
95
135
mA
Notes:
29. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
30. All clock outputs loaded with 6" 60
transmission lines with 20-pF capacitors.
31. W158 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
W158
Document #: 38-07164 Rev. *A
Page 8 of 13
3.3V AC Electrical Characteristics
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V 5%, f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[35]
Notes:
32. X1 input threshold voltage (typical) is V
DD
/2.
33. The W158 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
34. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
35. Period, jitter, offset, and skew measured on rising edge at 1.5V.
36. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Crystal Oscillator
V
TH
X1 Input threshold Voltage
[32]
1.65
V
C
LOAD
Load Capacitance, Imposed on
External Crystal
[33]
18
pF
C
IN,X1
X1 Input Capacitance
[34]
Pin X2 unconnected
28
pF
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
Except X1 and X2
5
pF
C
OUT
Output Pin Capacitance
6
pF
L
IN
Input Pin Inductance
7
nH
DC Electrical Characteristics:
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency
Note 36
66.6
MHz
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior
to frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
W158
Document #: 38-07164 Rev. *A
Page 9 of 13
Note:
37. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
PCI Clock Outputs, PCI_F and PCI1:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
t
P
Period
Measured on rising edge at 1.5V
[37]
30
ns
t
H
High Time
Duration of clock cycle above 2.4V
12
ns
t
L
Low Time
Duration of clock cycle below 0.4V
12
ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
500
ps
t
SK
Output Skew
Measured on rising edge at 1.5V
500
ps
t
O
3V66 to PCI Clock
Skew
Covers all 3V66/PCI outputs. Measured on rising edge at
1.5V. 3V66 leads PCI output.
1.5
3
ns
t
q
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at
1.5V. CPU leads PCI output.
1.5
4
ns
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
f
ST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
f
D
Deviation from 48 MHz
(48.008 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
W158
Document #: 38-07164 Rev. *A
Page 10 of 13
2.5V AC Electrical Characteristics
T
A
= 0C to +70C, V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5%
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[38]
Note:
38. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 133 MHz
CPU = 100 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.25V
7.5
7.65
10
10.2
ns
t
H
High Time
Duration of clock cycle above 2.0V
1.87
3.0
ns
t
L
Low Time
Duration of clock cycle below 0.4V
1.67
2.8
ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
150
150
ps
t
SK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 133 MHz
CPU = 100 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.25V
15
15.3
20
20.4
ns
t
H
High Time
Duration of clock cycle above 2.0V
5.25
7.5
ns
t
L
Low Time
Duration of clock cycle below 0.4V
5.05
7.3
ns
t
R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
20
20
W158
Document #: 38-07164 Rev. *A
Page 11 of 13
Note:
39. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
IOAPIC Clock Outputs, IOAPIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min
Typ
Max
Unit
f
Frequency
Note 39
16.67
MHz
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.25V
45
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
20
Ordering Information
Ordering Code
Package
Name
Package Type
W158
H
56-pin SSOP (300 mils)
W158
Document #: 38-07164 Rev. *A
Page 12 of 13
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
56-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
W158
Document #: 38-07164 Rev. *A
Page 13 of 13
Document Title: W158 Spread Spectrum System Frequency Synthesizer
Document Number: 38-07164
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110274
11/04/01
SZV
Change from Spec number: 38-00819 to 38-07164
*A
122805
12/14/02
RBI
Add Power up Requirements to Operating Conditions Information