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Электронный компонент: W162-19

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Spread AwareTM, Zero Delay Buffer
W162
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07150 Rev. **
Revised November 14, 2001
Features
Spread AwareTM--designed to work with SSFTG
reference signals
Two banks of four outputs, plus the fed back output
Outputs may be three-stated
Available in 16-pin SOIC or SSOP package
Extra strength output drive available (-19 version)
Internal feedback
Key Specifications
Operating Voltage: ............................................... 3.3V10%
Operating Range: ................................15 < f
OUT
< 133 MHz
Cycle-to-Cycle Jitter: .................................................. 250 ps
Output to Output Skew: ............................................. 150 ps
Propagation Delay: ..................................................... 150 ps
Table 1. Input Logic
SEL1
SEL0
QA0:3
QB0:3
PLL
QFB
0
0
Three-
State
Three-
State
Shutdown
Active
0
1
Active
Three-
State
Active,
Utilized
Active
1
0
Active
Active
Shutdown,
Bypassed
Active
1
1
Active
Active
Active,
Utilized
Active
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram
Pin Configuration
PLL
REF
MUX
QA1
QA2
QA3
QB0
QB1
SEL0
QB2
QB3
SEL1
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
16
15
14
13
12
11
10
9
REF
QA0
QA1
VDD
GND
QB0
QB1
SEL1
1
2
3
4
5
6
7
8
QFB
QA0
W162
Document #: 38-07150 Rev. **
Page 2 of 7
Overview
The W162 products are nine-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide eight copies of that same signal out.
Internal feedback is used to maximize the number of output
signals provided in the 16-pin package.
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress Application note titled, "EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs."
Functional Description
Logic inputs provide the user the ability to turn off one or both
banks of clocks when not in use, as described in Table 1. Dis-
abling a bank of unused outputs will reduce jitter and power
consumption, and will also reduce the amount of EMI generat-
ed by the W162.
These same inputs allow the user to bypass the PLL entirely if
so desired. When this is done, the device no longer acts as a
zero delay buffer, it simply reverts to a standard nine-output
clock driver.
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF
1
I
Reference Input: The output signals QA0:3 through QB0:3 will be synchro-
nized to this signal unless the device is programmed to bypass the PLL.
QFB
16
O
Feedback Output: This signal is used as the feedback internally to establish
the propagation delay of nearly 0.
QA0:3
2, 3, 14, 15
O
Outputs from Bank A: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
QB0:3
6, 7, 10, 11
O
Outputs from Bank B: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
VDD
4, 13
P
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise
for optimal jitter performance.
GND
5, 12
P
Ground Connections: Connect all grounds to the common system ground
plane.
SEL0:1
9, 8
I
Function Select Inputs: Tie to V
DD
(HIGH, 1) or GND (LOW, 0) as desired
per Table 1.
W162
Document #: 38-07150 Rev. **
Page 3 of 7
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics
: T
A
=0C to 70C, V
DD
= 3.3V 10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
I
DD
Supply Current
Unloaded, 100 MHz
40
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 12 mA (-19)
I
OL
= 8 mA (-9)
0.4
V
V
OH
Output High Voltage
I
OL
= 12 mA (-19)
I
OL
= 8 mA (-9)
2.4
V
I
IL
Input Low Current
V
IN
= 0V
500
A
I
IH
Input High Current
V
IN
= V
DD
10
A
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 3.3V 10%
Parameter
Description
Test Condition
Min
Typ
Max
Unit
f
IN
Input Frequency
15
133
MHz
f
OUT
Output Frequency
15-pF load
[5]
15
133
MHz
t
R
Output Rise Time (-09)
[1]
2.0 to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-19)
[1]
2.0 to 0.8V, 20-pF load
1.5
ns
t
F
Output Fall Time (-09)
[1]
2.0 to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-19)
[1]
2.0 to 0.8V, 20-pF load
1.5
ns
t
PD
FBIN to REF Skew
[2, 3]
Measured at V
DD
/2
150
ps
t
SK
Output to Output Skew
All outputs loaded equally
150
ps
t
D
Duty Cycle
15-pF load
[4]
45
50
55
%
t
LOCK
PLL Lock Time
Power supply stable
1.0
ms
t
JC
Jitter, Cycle-to-Cycle
250
ps
Notes:
1.
Long input rise and fall time will degrade skew and jitter performance.
2.
All AC specifications are measured with a 50
transmission line, load terminated with 50
to 1.4V.
3.
Skew is measured at V
DD
/2 on rising edges.
4.
Duty cycle is measured at V
DD
/2
5.
For the higher drive -19, the load is 20 pF.
W162
Document #: 38-07150 Rev. **
Page 4 of 7
Schematic
Ordering Information
Ordering Code
Option
Package
Name
Package Type
W162
-09, -19
G
H
16-pin Plastic SOIC (150-mil)
16-pin Plastic SSOP (150-mil)
9
2
3
1
4
7
6
8
5
16
13
14
15
10
11
12
V
DD
V
DD
10
F 0.1
F
Ferrite
Bead
Ferrite
Bead
V
DD
or GND (for desired operation mode)
V
DD
or GND (for desired operation mode)
Output
Output
Output
Output
Ground
Power
Power
Output
Ref In
Output
Output
Output
Output
Logic In
Logic In
Ground
10
F
0.1
F
W162
Document #: 38-07150 Rev. **
Page 5 of 7
Package Diagrams
16-pin SSOP Small Shrunk Outline Package (SSOP, 150-mil)