PRELIMINARY
133-MHz Spread Spectrum FTG for Pentium II Platforms
W167B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 2, 1999
Features
Maximized EMI Suppression using Cypress's Spread
Spectrum technology
Three copies of CPU outputs selectable frequency
Three copies of 3V66 selectable frequency output at
3.3V
Ten copies of PCI clocks (selectable frequency), 3.3V
One double strength 14.318-MHz reference output at
3.3V
One copy of 48-MHz USB clock
One copy of selectable 24-/48-MHz for SIO
One copy of CPU-divide-by-2 output as reference input
to Direct RambusTM Clock Generator (Cypress W134)
Three copies of IOAPIC
Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... V
DDQ2
= 2.5V5%
V
DDQ3
= 3.3V5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... 0.25%
CPU to 3V66 Output Offset: ............. 0.01.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.54.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.54.0 ns (CPU leads)
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Frequency
SEL133/
100#
SEL2 SEL1 SEL0
CPU
MHz
3V66
MHz
PCI
MHz
IOAPIC
MHz
1
1
1
1
133.3
66.7
33.3
16.7
1
1
1
0
138
69
34.5
17.3
1
1
0
1
143
71.5
35.8
17.9
1
1
0
0
148
74
37
18.5
1
0
1
1
150
75
37.5
18.8
1
0
1
0
152.5
76.3
38.1
19.1
1
0
0
1
155
77.5
38.8
19.4
1
0
0
0
160
80
40
20
0
1
1
1
100.2
66.8
33.4
16.7
0
1
1
0
105
70
35
17.5
0
1
0
1
114
76
38
19
0
1
0
0
120
80
40
20
0
0
1
1
66.8
66.8
33.4
16.7
0
0
1
0
124
82.7
41.3
20.7
0
0
0
1
128.5
64.3
32.1
16.1
0
0
0
0
133.9
67
33.5
16.7
Block Diagram
Pin Configuration
Note:
1.
Internal 250-k
pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
[1]
REF2X
CPU_[0:2]
CPUdiv2
3V66_[0:2]
XTAL
PLL 1
X2
X1
PCI_[2:9]
IOAPIC[0:2]
48MHz/SEL0*
PLL2
OSC
2
Power
2/1.5
Down
Logic
2
2
3
3
PWRDWN#
3
2
SIO/24_48#MHz
Serial
Logic
SEL133/100#
SCLK
SDATA
PCI0/SEL2*
PCI1/SEL1*
8
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
W167B
GND
VDDQ2
IOAPIC0
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
SDATA
VDDQ3
GND
PWRDN#*
SCLK
VDDQ3
SIO/24_48#MHz
*
48MHz/SEL0*
GND
SEL133/100#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IOAPIC1
Q#
VDDQ3
VDDQ2
VDDQ3
VDDQ2
VDDQ3
W167B
PRELIMINARY
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:2
35, 36, 39
O
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage
swing is controlled by voltage applied to VDDQ2.
SEL133/100#
25
I
SEL133/100#: Frequency selection input pin as shown in Table 1.
PCI0/SEL2
7
I/O
PCI Clock Output 0 and Selection Bit 2: As an output, this pin works in
conjunction with PCI2:9. When an input, this pin functions as part of the fre-
quency selection address (see Table 1).
PCI1/SEL1
8
I/O
PCI Clock Output 1 and Selection Bit 1: As an output, this pin works in
conjunction with PCI2:9. When an input, this pin functions as part of the fre-
quency selection address (see Table 1).
PCI2:9
10, 11, 12,
13, 15, 16,
18, 19
O
PCI Clock Outputs 2 through 9: Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:2
21, 22, 23
O
66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by
voltage applied to VDDQ3.
CPUdiv2
42
O
CPU-Divide-By-2 Output: This serves as a reference input signal for Direct
Rambus
Clock Generator (Cypress W134). The output voltage is determined
by VDDQ2.
IOAPIC0:2
46, 45, 1
O
I/O APIC Clock Output 0 through 2: Provide outputs synchronous to CPU
clock. See Table 1 and Table 5 for their relation to other system clock outputs.
48MHZ/SEL0
27
I/O
48-MHz Output and Selection Bit 0: Fixed clock output that defaults to
48-MHz following device power-up. When an input, this pin functions as part of
the frequency selection address (see Table 1).
SIO/24_48#MHz
28
I/O
Super I/O Reference Clock Output and SIO Clock Frequency Select: Fixed
clock output that provides the reference input clock to a Super I/O device. The
output frequency is determined by the input value on this pin during power up.
If input is sampled HIGH, the output operates at 24 MHz, otherwise, the output
operates at 48 MHz.
REF2X
2
O
Fixed 14.318-MHz Output: With double strength driving capability.
PWRDWN#
31
I
Power Down Control
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
SDATA
34
I/O
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
SCLK
30
I
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDDQ2
37, 40, 43, 47
P
Power Connection: Connected to 2.5V power supply.
VDDQ3
3, 9, 17, 24,
29, 33
P
Power Connection: Connected to 3.3V supply.
GND
6, 14, 20, 26,
32, 38, 41,
44, 48
G
Ground Connection: Connect all ground pins to the common system ground
plane.
W167B
PRELIMINARY
3
Overview
The W167B, a motherboard clock synthesizer, provides 2.5V
CPU clock outputs for advanced CPU and a CPU-divide-by-2
reference frequency for Direct Rambus
Clock Generator (such
as Cypress W134) interface. Fixed output frequencies are pro-
vided for other system functions.
I/O Pin Operation
Pins 7, 8, 27, and 28 are dual-purpose l/O pins. Upon power-
up these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins then become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
each l/O pin and ground or V
DD3
. Connection to ground sets a
latch to "0", connection to V
DD3
sets a latch to "1". Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connection.
Upon W167B power up, the first 2 ms of operation is used for
input logic selection. During this period, these dual-purpose
I/O pins are three-stated, allowing the output strapping resistor
on each l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic 0 or 1 condition of each
l/O pin is then latched. Next, the output buffers are enabled,
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when V
DD
reaches 2.0V. The input bits can only
be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock outputs is <40
(nominal) which is minimally
affected by the 10-k
strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered assuming
that V
DD
has stabilized. If V
DD
has not yet reached full value,
output frequency initially may be below target but will increase
to target once V
DD
voltage has stabilized. In either case, a
short output clock cycle may be produced from the CPU clock
outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W167B
V
DD
Clock Load
R
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W167B
V
DD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
W167B
PRELIMINARY
4
CPU/PCI Frequency Selection
CPU frequency is selected with I/O pins 7, 8, 27, (SEL2/PCI0,
SEL1/PCI1, 48MHz/SEL0, respectively) and input pin 25
(SEL133/100#). Refer to Table 1 for CPU/PCI frequency pro-
gramming information. Additional frequency selections are
available through the serial data interface. Refer to Table 5 on
page 9.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The W167B outputs are CMOS-type which provide rail-
to-rail output swing.
Crystal Oscillator
The W167B requires one input reference clock to synthesize
all output frequencies. The reference clock can be either an
externally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W167B incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 18 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
18 pF should be used. This will typically yield reference fre-
quency accuracies within 100 ppm.
W167B
PRELIMINARY
5
Spread Spectrum Feature
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5% downspread. Figure 4
details the Cypress spreading pattern. Cypress does offer op-
tions with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Figure 3. Typical Clock and SSFTG Comparison
100%
60%
20%
80%
40%
0%
20%
40%
60%
80%
100%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
Time
Fr
e
q
ue
nc
y
S
h
i
f
t
Figure 4. Typical Modulation Profile
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