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Электронный компонент: W183-5G

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Full Feature Peak Reducing EMI Solution
W183
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07158 Rev. *A
Revised September 25, 2001
Features
Cypress PREMISTM
family offering
Generates an EMI optimized clocking signal at the out-
put
Selectable output frequency range
Single 1.25%, 3.75% down or center spread output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 14-pin SOIC (Small Outline Integrated
Circuit)
Key Specifications
Supply Voltages: ...........................................V
DD
= 3.3V5%
or V
DD
= 5V10%
Frequency Range: ............................ 28 MHz
F
in
75 MHz
Crystal Reference Range:................. 28 MHz
F
in
40 MHz
Cycle to Cycle Jitter: ....................................... 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Table 1. Modulation Width Selection
SS%
W183
Output
W183-5
Output
0
F
in
F
out
F
in
1.25%
F
in
+ 0.625%
F
in
0.625%
1
F
in
F
out
F
in
3.75%
F
in
+ 1.875%
F
in
1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
0
0
28 MHz
F
IN
38 MHz
0
1
38 MHz
F
IN
48 MHz
1
0
46 MHz
F
IN
60 MHz
1
1
58 MHz
F
IN
75 MHz
PREMIS is a trademark of Cypress Semiconductor Corporation.
Simplified Block Diagram
Pin Configuration
SOIC
W
183/
W
183-5
14
13
12
11
1
2
3
4
FS2
CLKIN or X1
NC or X2
GND
REFOUT
OE#
SSON#
Reset
5
6
7
8
9
10
VDD
VDD
CLKOUT
GND
SS%
FS1
Spread Spectrum
W183
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W183
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
40 MHz
Max
W183
Document #: 38-07158 Rev. *A
Page 2 of 9
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CLKOUT
8
O
Output Modulated Frequency: Frequency modulated copy of the input clock
(SSON# asserted).
REFOUT
14
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature regardless of the state
of logic input SSON#.
CLKIN or X1
2
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
3
I
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference, this pin must be left unconnected.
SSON#
12
I
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
SS%
6
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistor.
OE#
13
I
Output Enable (Active LOW): When this pin is held HIGH, the output buffers
are placed in a high-impedance mode. This pin has an internal pull-down re-
sistor.
Reset
11
I
Modulation Profile Restart: A rising edge on this input restarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
FS1:2
7, 1
I
Frequency Selection Bits: These pins select the frequency range of opera-
tion. Refer to Table 2. These pins have internal pull-up resistors.
VDD
9, 10
P
Power Connection: Connected to 3.3V or 5V power supply.
GND
4, 5
G
Ground Connection: Connect all ground pins to the common ground plane.
W183
Document #: 38-07158 Rev. *A
Page 3 of 9
Overview
The W183 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Functional Description
The W183 uses a phase-locked loop (PLL) to frequency mod-
ulate an input clock. The result is an output clock whose fre-
quency is slowly swept over a narrow band near the input sig-
nal. The basic circuit topology is shown in Figure 1. The input
reference signal is divided by Q and fed to the phase detector.
A signal from the VCO is divided by P and fed back to the
phase detector also. The PLL will force the frequency of the
VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W183 the output
frequency is equal to the input frequency.) The unique feature
of the Spread Spectrum Frequency Timing Generator is that a
modulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
V
DD
Q
P
Clock Input
Reference Input
(EMI suppressed)
Figure 1. Functional Block Diagram
W183
Document #: 38-07158 Rev. *A
Page 4 of 9
Spread Spectrum Frequency Timing
Generation
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions.Figure
3
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
SSFTG
Typical Clock
Frequency Span (MHz)
Amp
litu
d
e
(d
B)
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Frequency Span (MHz)
Down Spread
Am
p
lit
u
d
e
(
d
B)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
F
R
EQUENCY
Figure 3. Typical Modulation Profile
W183
Document #: 38-07158 Rev. *A
Page 5 of 9
Absolute Maximum Ratings
[1]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics
: 0C < T
A
< 70C, V
DD
= 3.3V 5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
18
32
mA
t
ON
Power Up Time
First locked clock cycle after Power
Good
5
ms
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.4
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 2
50
A
I
IH
Input High Current
Note 2
50
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 3.3V
15
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 3.3V
15
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
500
k
Z
OUT
Clock Output Impedance
25
Note:
1.
Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
2.
Inputs FS1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.