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Электронный компонент: W224BX

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133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
W224B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07191 Rev. *A
Revised December 22, 2002
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology (0.5% and 1.0%)
Single chip system FTG for Mobile Intel
Platforms
Three CPU outputs
Seven copies of PCI clock (one Free Running)
Seven SDRAM clock (one DCLK for Memory Hub)
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
Three 3V66 Hublink/AGP outputs
One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
Two APIC outputs
One buffered reference output
Supports frequencies up to 133 MHz
Supports 5% and 10% overclocking
SMBus interface for programming
Power management control inputs
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU Output Skew: ...................................................... 150 ps
3V66 Output Skew: ..................................................... 175 ps
APIC, SDRAM Output Skew: ...................................... 250 ps
PCI Output Skew: ........................................................ 500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: .......... 3.3V5%
VDDQ2 (CPU, APIC):.............................................. 2.5V5%
Intel is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Functions
TEST#
FS1
FS0
CPU
SDRAM
0
x
0
Three-state
Three-state
0
x
1
Test
Test
1
0
0
66 MHz
100 MHz
1
0
1
100 MHz
100 MHz
1
1
0
133 MHz
133 MHz
1
1
1
133 MHz
100 MHz
Block Diagram
VDD_REF
VDD_APIC
APIC0:1
CPU0
CPU_F1:2
PCI_F
XTAL
PLL Ref Freq
X2
X1
REF
VDD_PCI
USB (48MHz)
VCH_CLK
OSC
VDD_CPU
CPU_STP#
SCLK
PCI1:6
PCI_STP#
Stop
Clock
Control
Stop
Clock
Control
PLL 1
SMBus
Logic
DOT (48MHz)
PLL2
PWR_DWN#
FS0:1
VDD_48MHz
SDATA
VDD_SDRAM
SDRAM0:5
DCLK
VDD_3V66
3V66_0:1
3V66_AGP
Divider
Network
REF
VDD_REF
X1
X2
GND_REF
GND_3V66
3V66_0
3V66_1
3V66_AGP
VDD_3V66
*PCI_STP#
PCI_F
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
PCI6
GND_PCI
VDD_CORE
GND_CORE
GND_48MHz
W2
24
B
GND_APIC
APIC0
APIC1
VDD_APIC
CPU0
VDD_CPU
CPU_F1
CPU_F2
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
DCLK
VDD_SDRAM
VCH_CLK
VDD_VCH
CPU_STP#*
TEST#*
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
32
31
30
29
USB
DOT
VDD_48MHz
FS0
PWR_DWN#*
SCLK
SDATA
FS1
Note:
1.
Internal pull-up resistors present on inputs marked with [*].
Design should not rely solely on internal pull-up to set I/O pins
HIGH.
Pin Configuration
[
1]
W224B
Document #: 38-07191 Rev. *A
Page 2 of 18
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU0,
CPU_F1:2
52, 50, 49
O
CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial
input interface. The CPU0 output is gated by the CLK_STOP# input.
PCI1:6, PCI_F
13, 15, 16, 18,
19, 20, 12
O
33-MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by
the PCI_STOP# input.
APIC0:1
55, 54
O
APIC Output: 2.5V fixed 33.33-MHz clock. This output is synchronous to the
CPU clock.
SDRAM0:5,
DCLK
46, 45, 43, 42,
40, 39, 38
O
SDRAM Output Clocks: 3.3V outputs running at either 100MHz or 133MHz
depending on the setting of FS0:1 inputs. DCLK is a free-running clock.
3V66_0:1,
3V66_AGP
7, 8, 9
O
66MHz Clock Outputs: 3.3V fixed 66-MHz clock.
USB
25
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock out-
put.
DOT
26
O
Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal.
REF
1
O
Reference Clock: 3.3V 14.318-MHz clock output.
VCH_CLK
36
O
Video Control Hub Clock Output: 3.3V selectable 48MHz non-spread spec-
trum or 66.67 MHz spread spectrum clock output.
PWR_DWN#
32
I
Power Down Control: 3.3V LVTTL-compatible input that places the device in
power down mode when held low.
CPU_STP#
34
I
CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0
clock. Output remains in the low state.
PCI_STP#
11
I
PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks.
Output remains in the low state.
TEST#
33
I
Test Mode Control: 3.3V LVTTL-compatible input to place the device into test
mode.
FS0:1
28, 29
I
Frequency Selection Input: 3.3V LVTTL-compatible input used to select the
CPU and SDRAM frequencies. See Frequency Table.
SCLK
31
I
SMBus Clock Input: Clock pin for SMBus circuitry.
SDATA
30
I/O
SMBus Data Input: Data pin for SMBus circuitry.
X1
3
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
4
O
Crystal Connection: Connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
VDD_REF,
VDD_3V66,
VDD _PCI,
VDD_48MHz,
VDD_VCH,
VDD_SDRAM,
VDD_SDRAM
2, 10, 17, 27,
35, 37, 44
P
3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM
outputs buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
VDD_APIC,
VDD_CPU
51, 53
P
2.5V Power Connection: Power supply for APIC and CPU output buffers. Con-
nect to 2.5V.
W224B
Document #: 38-07191 Rev. *A
Page 3 of 18
Overview
The W224 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel architec-
ture platform using graphics integrated core logic.
CPU/SDRAM Frequency Selection
CPU output frequency is selected through pins 28 and 29. For
CPU/SDRAM frequency programming information, refer to Ta-
ble 2
. Alternatively, frequency selections are available through
the serial data interface.
Notes:
2.
Provided for board-level "bed of nails" testing.
3.
TCLK is a test clock overdriven on the XTAL_IN input during test mode.
4.
Required for DC output impedance verification.
5.
"Normal" mode of operation.
6.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
GND_REF,
GND_3V66,
GND_PCI,
GND_PCI,
GND_48MHz,
GND_SDRAM,
GND_SDRAM,
GND_CPU,
GND_APIC
5, 6, 14, 21, 24,
41, 47, 48, 56
G
Ground Connection: Connect all ground pins to the common system ground
plane.
VDD_CORE
22
P
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry.
Connect to 3.3V.
GND_CORE
23
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
Table 2. Frequency Select Truth Table
TEST#
FS1
FS0
CPU
SDRAM
3V66
PCI
48MHz
REF
APIC
Notes
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
0
X
1
TCLK/2
TCLK/2
TCLK/3
TCLK/6
TCLK/2
TCLK
TCLK/6
3, 4
1
0
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
5, 6, 7
1
0
1
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
5, 6, 7
1
1
0
133 MHz
133 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
5, 6, 7
1
1
1
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
5, 6, 7
W224B
Document #: 38-07191 Rev. *A
Page 4 of 18
Offsets Among Clock Signal Groups
Figure 1 and Figure 2 represent the phase relationship among
the different groups of clock outputs from W224 when it is pro-
viding a 66-MHz CPU clock and a 100-MHz CPU clock, re-
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
Table 3. 66 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to 3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
2.5 ns
7.5 ns
0.0 ns
1.53.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 1. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
Figure 2. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM Clock)
W224B
Document #: 38-07191 Rev. *A
Page 5 of 18
Table 4. 100-MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to
3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
5.0 ns
5.0ns
0.0 ns
1.53.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 3. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
Table 5. 133-MHz/SDRAM 100-MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to 3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
0.0 ns
0.0 ns
0.0 ns
1.53.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 4. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 133-MHz
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz