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Электронный компонент: W233

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PRELIMINARY
Spread Spectrum FTG for VIA Mobile K7 Chipset
W233
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07250 Rev. **
Revised September 27, 2001
Features
Maximized EMI Suppression using Cypress's Spread
Spectrum technology
Single-chip system frequency synthesizer for VIA Mo-
bile K7 chipset
Two copies of CPU output
Seven copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Three buffered reference outputs
Six SDRAM outputs provide support for three SODIMMs
Supports frequencies up to 166 MHz
SMBus interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DD
: ........................................................................ 3.3V5%
SDRAMIN to SDRAM0:5 Delay: ............................2.0 ns typ.
Table 1. Pin Selectable Frequency
Input Address
CPU
(MHz)
PCI
(MHz)
Spread
Spectrum
FS3
FS2
FS1
FS0
1
1
1
1
133.3
33.3
OFF
1
1
1
0
100.0
33.3
OFF
1
1
0
1
133.3
33.3
0.5%
1
1
0
0
100.0
33.3
0.5%
1
0
1
1
133.3
33.3
0.5%
1
0
1
0
100.0
33.3
0.5%
1
0
0
1
133.3
33.3
0.25%
1
0
0
0
100.0
33.3
0.25%
0
1
1
1
95.0
31.7
OFF
0
1
1
0
102.0
34.0
OFF
0
1
0
1
104.0
34.6
OFF
0
1
0
0
106.0
35.3
OFF
0
0
1
1
108.0
36.0
OFF
0
0
1
0
110.0
36.6
OFF
0
0
0
1
111.0
37.0
OFF
0
0
0
0
112.0
37.3
OFF
Block Diagram
Pin Configuration
[1]
Note:
1.
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
VDD_REF
REF0_2X
PCI0/FS1
XTAL
PLL 1
X2
X1
REF1
VDD_PCI
PCI2
PCI3
PCI4
48MHz/FS0
*SEL24_48#/24_48MHz
PLL2
2,3,4
OSC
CLK_STOP#
VDD_48MHz
PCI5
SMBus
SDATA
Logic
SCLK
I/O Pin
Control
SDRAM0:5
SDRAMIN
7
VDD_SDRAM
PCI1
CPUT0_F
2
CPU_CS
CPUC0_F
VDD_REF
X1
X2
*FS2/PCI_F
*FS1/PCI0
VDD_PCI
GND_PCI
PCI1
PCI2
PCI3
PCI4
PCI5
GND_PCI
VDD_PCI
PCI6
*SDRAM_STOP#
*PCI_STOP#
SDRAMIN
VDD_CORE
GND_CORE
GND_48MHz
*FS0/48MHz
*SEL24_48#/24_48MHz
VDD_48MHz
W2
33
REF0_2X
REF1
REF2/FS3*
GND_REF
GND_CPU
VDD_CPU
CPU_CS
CPUT0_F
CPUC0_F
CPU_STOP#*
STOP_CLK#*
SDRAM0
SDRAM1
VDD_SDRAM
GND_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
VDD_SDRAM
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PCI6
REF2/FS3*
Stop
Clock
Control
CPU_STOP#
Stop
Clock
Control
PCI_STOP#
PCI_F/FS2
VDD_CPU
Stop
Clock
Control
SDRAM_F
SDRAM_STOP#
Stop
Clock
Control
W233
PRELIMINARY
Document #: 38-07250 Rev. **
Page 2 of 16
Pin Definitions
Pin Name
Pin No.
Pin Type
Pin Description
CPUC0_F,
CPUT0_F,
40, 41
O
(open-
drain)
CPU Clock Output 0: CPUT0_F and CPUC0_F are the differential CPU clock
outputs for the K7 processor.
CPU_CS
42
O
CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the
chipset. It has the same phase relationship as CPUT0_F.
PCI1:6
8, 9, 10, 11,
12, 15
O
PCI Clock Outputs 1 through 6: These six PCI clock outputs are controlled
by the PCI_STP# control pin. Frequency is set by FS0:3 inputs or through serial
input interface, see Tables 1 and 5 for details. Output voltage swing is con-
trolled by voltage applied to VDDQ3.
FS1/PCI0
5
I/O
Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set
by FS0:3 inputs or through serial input interface. This pin also serves as a
PCI_STP# strap option to determine device operating frequency as described
in Table 1.
FS2/PCI_F
4
I/O
Fixed PCI Clock Output/Frequency Select 2: As an output, frequency is set
by the FS0:3 inputs or through serial input interface, see Tables 1 and 5. This
output is controlled by the STOP_CLK# input. This pin also serves as a power-
on strap option to determine device operating frequency as described in Table
2
.
STOP_CLK#
38
I
STOP_CLK# Input: LVTTL-compatible input that places the device in stop-
clock mode when held LOW. In stop-clock mode, CPUT0_F and CPUC0_F will
be active and all the other output clocks will be driven LOW. STOP_CLK# is an
asynchronous input. W233 will not complete the current clock cycle when
STOP_CLK# is being driven LOW.
48MHz/FS0
22
I/O
48-MHz Output/Frequency Select 0: 48 MHz is provided in normal operation.
In standard PC systems, this output can be used as the reference for the
Universal Serial Bus host controller. This pin also serves as a power on strap
option to determine device operating frequency as described in Table 1.
SEL24_48#/24_
48MHz
23
I/O
24_48-MHz Output/Frequency Select 24 or 48 MHz: In standard PC sys-
tems, this output can be used as the clock input for a Super I/O chip. The output
frequency is controlled by Configuration Byte 3 bit[6] or SEL 24_48 MHz stop
option. The default output frequency is 24 MHz. This pin also serves as a
power-on strap option to determine device operating frequency.
REF1
47
I/O
Reference Clock Output 1: 3.3V 14.318-MHz output clock.
REF2/FS3
46
I/O
Reference Clock Output 2/Frequency Select 3: 3.3V 14.318-MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency.
REF0_2X
48
O
Reference Clock Output 0: 3.3V 14.318-MHz output clock with double drive
strength.
SDRAMIN
18
I
Buffered Input Pin: The signal provided to this input pin is buffered to seven
outputs (SDRAM0:5 & SDRAM_F).
SDRAM0:5,
SDRAM_F
37, 36, 33,
32, 29, 28, 27
O
Buffered Outputs: These seven dedicated outputs provide copies of the sig-
nal provided at the SDRAMIN input. The swing is set by VDD, and they are
deactivated when SDRAM_STOP# input is set LOW, except SDRAM_F.
SCLK
26
I
Clock pin for SMBus circuitry.
SDATA
25
I/O
Data pin for SMBus circuitry.
X1
2
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
3
O
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
SDRAM_STOP#
16
I
SDRAM Stop Input: LVTTL compatible input that disables the SDRAM output
clocks, except SDRAM_F.
W233
PRELIMINARY
Document #: 38-07250 Rev. **
Page 3 of 16
PCI_STOP#
17
I
PCI Stop Input: LVTTL compatible input that disables the PCI output clocks,
except PCI_F.
CPU_STOP#
39
I
CPU Stop Input: LVTTL compatible input that disables the CPU output clocks,
except CPUT0_F and CPUC0_F.
VDD_REF,
VDD_PCI,
VDD_CORE,
VDD_48MHz,
VDD_SDRAM,
VDD_CPU
1, 6, 14, 19,
24, 30, 35, 43
P
Power Connection: Power supply for core logic, PLL circuitry, SDRAM out-
puts, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output.
Connect to 3.3V supply
GND_PCI,
GND_CORE,
GND_48MHz,
GND_SDRAM,
GND_CPU,
GND_REF
7, 13, 20, 21,
31, 34, 44, 45
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Definitions
(continued)
Pin Name
Pin No.
Pin Type
Pin Description
W233
PRELIMINARY
Document #: 38-07250 Rev. **
Page 4 of 16
Overview
The W233 was developed as a single-chip device to meet the
clocking needs of VIA K7 core logic chip sets. In addition to the
typical outputs provided by a standard FTG, the W233 adds a
seventh output buffer, supporting SDRAM DIMM modules in
conjunction with the chipset.
Cypress's proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en-
abled, this feature reduces the peak EMI measurements of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 4, 5, 22, 23, and 46 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to "0," connection to V
DD
sets a latch to "1." Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W233 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (4, 5,
22, 23, 46) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull the pins and their associated ca-
pacitive clock load to either a logic HIGH or LOW state. At the
end of the 2-ms period, the established logic "0" or "1" condi-
tion of the l/O pin is latched. Next the output buffer is enabled
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when V
DD
reaches 2.0V. The input bits can only
be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock outputs is <40
(nominal), which is minimally
affected by the 10-k
strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W233
V
DD
Clock Load
R
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W233
V
DD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
Resistor Value R
W233
PRELIMINARY
Document #: 38-07250 Rev. **
Page 5 of 16
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is specified in Table 5. Figure 4
details the Cypress spreading pattern. Cypress does offer op-
tions with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate data bytes of the SMBus data stream.
Refer to Table 5 for more details.
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
SSFTG
Typical Clock
Amp
litude
(dB)
Spread
Spectrum
Enabled
EMI Reduction
Non-
Spread
Speactrum
Am
pl
i
t
ud
e (
d
B)
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 4. Typical Modulation Profile
MAX (0%)
MIN (0.5%)
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
FREQUENCY