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Электронный компонент: W234X

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Dual Direct RambusTM Clock Generator
W234
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07232 Rev. *B
Revised December 21, 2002
Features
Differential clock source for Direct RambusTM
memory
subsystem for up to 1.6-Gb/s serial data transfer rate
Provide synchronization flexibility: the Rambus
Chan-
nel can optionally be synchronous to an external sys-
tem or processor clock
Power managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
Works with Cypress CY2210-2, CY2210-3, CY2215,
W133, W158, W159, W161, and W167B to support Intel
architecture platforms
Low-power CMOS design packaged in a 28-pin, 173-mil
TSSOP package
Overview
The Cypress W234 provides dual channel differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
Key Specifications
Supply Voltage: ................................... V
DD
= 3.3V 0.165V
Operating Temperature: ................................... 0C to +70C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................V
DD
+ 0.5V
Maximum Input Frequency: ..................................... 100 MHz
Output Duty Cycle: .................................. 40/60% worst case
Output Type: ........................... Rambus signaling level (RSL)
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.
Intel is a registered trademark of Intel Corporation.
Block Diagram
Pin Configuration
PLL
Phase
MULT0:2
REFCLK
Logic
Logic
Test
Alignment
STOP#
S0:2
CLK0
CLK0#
Phase
Alignment
PWR_DWN#
CLK1
CLK1#
PCLKM0
SYNCLKN0
PCLKM1
SYNCLKN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDIR
REFCLK
VDD
SYNCLKN0
PCLKM0
GND
GND
VDD
SYNCLKN1
PCLKM1
VDD
VDDIPD
STOP#
PWR_DWN#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S0
S1
S2
GND
CLK0#
CLK0
VDD
VDD
CLK1
CLK1#
GND
MULT0
MULT1
MULT2
Logic
Output
Output
W234
Document #: 38-07232 Rev. *B
Page 2 of 14
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
REFCLK
2
I
Reference Clock Input: Reference clock input, normally supplied by a system
frequency synthesizer (Cypress W133).
PCLKM0:1
5, 10
I
Phase Detector Input 0:1: The phase difference between this signal and SYN-
CLKN is used to synchronize the Rambus Channel Clock with the system clock.
Both PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory
controller. If the Gear Ratio Logic is not used, this pin would be connected to
ground.
SYNCLKN0:1
4, 9
I
Phase Detector Input 0:1: The phase difference between this signal and PCLKM
is used to synchronize the Rambus Channel Clock with the system clock. Both
PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-
troller. If the Gear Ratio Logic is not used, this pin would be connected to ground.
STOP#
13
I
Clock Output Enable: When this input is driven to active LOW, it disables the
differential Rambus Channel clocks.
PWR_DWN#
14
I
Active LOW Power-Down: When this input is driven to active LOW, it disables
the differential Rambus Channel clocks and places the W234 in Power-Down
mode.
MULT 0:2
17, 16, 15
I
PLL Multiplier Select: These inputs select the PLL prescaler and feedback divid-
ers to determine the multiply ratio for the PLL for the input REFCLK.
CLK0, CLK0#,
CLK1, CLK1#
23, 24, 20,
19
O
Complementary Output Clock: Differential Rambus Channel clock outputs.
S0, S1, S2
28, 27, 26
I
Mode Control Input: These inputs control the operating mode of the W234.
VDDIR
1
RefV
Reference for Refclk: Voltage reference for input reference clock.
VDDIPD
12
RefV
Reference for Phase Detector: Voltage reference for phase detector inputs and
STOP#.
VDD
3, 7, 11, 21,
22
P
Power Connection: Power supply for core logic and output buffers. Connected to
3.3V supply.
GND
6, 8, 18, 25
G
Ground Connection: Connect all ground pins to the common system ground
plane.
MULT1
0
0
1
1
0
0
1
1
MULT0
0
0
0
0
1
1
1
1
A
4
9
6
TBD
8
16
8
TBD
MULT2
0
1
0
1
0
1
0
1
B
1
2
1
TBD
3
3
1
TBD
S1
0
0
1
0
0
1
1
S0
0
1
1
0
1
1
0
MODE
Normal
Bypass
Test
Vendor Test A
Vendor Test B
Reserved
Output Test (OE)
S2
0
0
0
1
1
1
X
W234
Document #: 38-07232 Rev. *B
Page 3 of 14
DDLL System Architecture and Gear Ratio Logic
Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys-
tem architecture, including the main system clock source, the
Direct Rambus clock generator (DRCG), and the core logic
that contains the Rambus Access Cell (RAC), the Rambus
Memory Controller (RMC), and the Gear Ratio Logic. (This
diagram abstractly represents the differential clocks as a sin-
gle Busclk wire.)
The purpose of the DDLL is to frequency-lock and phase-align
the core logic and Rambus clocks (PCLK and SYNCLK) at the
RMC/RAC boundary in order to allow data transfers without
incurring additional latency. In the DDLL architecture, a PLL is
used to generate the desired Busclk frequency, while a distrib-
uted loop forms a DLL to align the phase of Pclk and Synclk at
the RMC/RAC boundary.
The main clock source drives the system clock (Pclk) to the
core logic, and also drives the reference clock (Refclk) to the
DRCG. For typical Intel architecture platforms, Refclk will be
half the CPU front side bus frequency. A PLL inside the DRCG
multiplies Refclk to generate the desired frequency for Busclk,
and Busclk is driven through a terminated transmission line
(Rambus Channel). At the mid-point of the channel, the RAC
senses Busclk using its own DLL for clock alignment, followed
by a fixed divide-by-4 that generates Synclk.
Pclk is the clock used in the memory controller (RMC) in the
core logic, and Synclk is the clock used at the core logic inter-
face of the RAC. The DDLL together with the Gear Ratio Logic
enables users to exchange data directly from the Pclk domain
to the Synclk domain without incurring additional latency for
synchronization. In general, Pclk and Synclk can be of differ-
ent frequencies, so the Gear Ratio Logic must select the ap-
propriate M and N dividers such that the frequencies of Pclk/M
and Synclk/N are equal. In one interesting example,
Pclk=133 MHz, Synclk=100 MHz, and M=4 while N=3, giving
Pclk/M=Synclk/N=33 MHz. This example of the clock wave-
forms with the Gear Ratio Logic is shown in Figure 2.
The output clocks from the Gear Ratio Logic, Pclk/M, and Syn-
clk/N, are output from the core logic and routed to the DRCG
Phase Detector (
D
) inputs. The routing of Pclk/M and Syn-
clk/N must be matched in the core logic as well as on the
board.
After comparing the phase of Pclk/M vs. Synclk/N, the DRCG
Phase Detector (
D
) drives a phase aligner that adjusts the
phase of the DRCG output clock, Busclk. Since everything
else in the distributed loop is fixed delay, adjusting Busclk ad-
justs the phase of Synclk and thus the phase of Synclk/N. In
this manner the distributed loop adjusts the phase of Synclk/N
to match that of Pclk/M, nulling the phase error at the input of
the DRCG Phase Detector (
D
). When the clocks are aligned,
data can be exchanged directly from the Pclk domain to the
Synclk domain.
Figure 1. DDLL System Architecture.
W234
Refclk
PLL
Phase
Align
D
4
DLL
RAC
RMC
M N
Gear
Ratio
Logic
Pclk
Busclk
Synclk
P
c
lk
/M
Sy
n
c
l
k
/
N
W133
W158
W159
W161
W167B
CY2210-2
CY2215
CY2210-3
Pclk
Synclk
Pclk/M =
Synclk/N
Figure 2. Gear Ratio Timing Diagram.
W234
Document #: 38-07232 Rev. *B
Page 4 of 14
Phase Detector Signals
The DRCG Phase Detector (
D
) receives two inputs from the
core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M
and N dividers in the core logic are chosen so that the frequen-
cies of PCLKM and SYNCLKN are identical. The Phase De-
tector (
D
) detects the phase difference between the two input
clocks, and drives the DRCG Phase Aligner to null the input
phase error through the distributed loop. When the loop is
locked, the input phase error between PCLKM and SYNCLKN
is within the specification t
ERR,PD
given in Table 13 after the
lock time given in the State Transition Section.
The Phase Detector (
D
) aligns the rising edge of PCLKM to
the rising edge of SYNCLKN. The duty cycle of the phase de-
tector input clocks will be within the specification DC
IN,PD
giv-
en in Table 12. Because the duty cycles of the two phase de-
tector input clocks will not necessarily be identical, the falling
edges of PCLKM and SYNCLKN may not be aligned when the
rising edges are aligned.
The voltage levels of the PCLKM and SYNCLKN signals are
determined by the controller. The pin VDDIPD is used as the
voltage reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PCLKM and SYN-
CLKN are not used, those inputs must be grounded.
Selection Logic
Table 1 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLClk=Refclk*A/B.
Table 2 shows the logic for enabling the clock outputs, using
the STOP# input signal. When STOP# is HIGH, the DRCG is
in its normal mode, and CLK and CLK# are complementary
outputs following the Phase Aligner output (PAclk). When
STOP# is LOW, the DRCG is in the Clk Stop mode, the output
clock drivers are disabled (set to Hi-Z), and the CLK and CLK#
settle to the DC voltage V
X,STOP
as given in Table 13. The level
of V
X,STOP
is set by an external resistor network.
Table 3 shows the logic for selecting the Bypass and Test
modes. The select bits, S0, S1, and S2 control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the REFCLK input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the CLK and CLK# outputs are put into a high-
impedance state (Hi-Z). This can be used for component test-
ing and for board-level testing.
Figure 3. DDLL Including Details of DRCG.
W234
Refclk
W133
PLL
Phase
Align
D
4
DLL
RAC
RMC
M N
Gear
Ratio
Logic
Pclk
Busclk
Synclk
Pc
l
k
/
M
S
y
n
c
lk
/N
S0/S1/S2 STOP#
W158
W159
W161
W167B
CY2210-2
CY2215
CY2210-3
Table 1. PLL Divider Selection
MULT0
MULT1
MULT2
A
B
0
0
0
4
1
0
0
1
9
2
0
1
0
6
1
0
1
1
TBD
1
0
0
8
3
1
0
1
16
3
1
1
0
8
1
1
1
1
TBD
Table 2. Clk Stop Mode Selection
Mode
STOP#
CLK
CLK#
Normal
1
PACLK
PACLK#
Clk Stop
0
V
X,STOP
V
X,STOP
W234
Document #: 38-07232 Rev. *B
Page 5 of 14
Table 4 shows the logic for selecting the Power-Down mode,
using the PWR_DWN# input signal. PWR_DWN# is active
LOW (enabled when 0). When PWR_DWN# is disabled, the
DRCG is in its normal mode. When PWR_DWN# is enabled,
the DRCG is put into a powered-off state, and the CLK and
CLK# outputs are three-stated.
Table of Frequencies and Gear Ratios
Table 5 shows several supported Pclk and Busclk frequencies,
the corresponding A and B dividers required in the DRCG PLL,
and the corresponding M and N dividers in the gear ratio logic.
The column Ratio gives the Gear Ratio as defined Pclk/Synclk
(same as M and N). The column F@PD gives the divided down
frequency (in MHz) at the Phase Detector (
D
), where
F@PD = PCLK/M = SYNCLK/N.
State Transitions
The clock source has three fundamental operating states.
Figure 4 shows the state diagram with each transition labelled
A through H. Note that the clock source output may NOT be
glitch-free during state transitions.
Upon powering up the device, the device can enter any state,
depending on the settings of the control signals, PWR_DWN#
and STOP#.
In Power-Down mode, the clock source is powered down with
the control signal, PWR_DWN#, equal to 0. The control sig-
nals S0, S1 and S2 must be stable before power is applied to
the device, and can only be changed in Power-Down mode
(PWR_DWN#=0). The reference inputs, VDDIR and VDDIPD,
may remain on or may be grounded during the Power-Down
mode.
The control signals MULT0, MULT1, and MULT2 can be used
in two ways. If they are changed during Power-Down mode,
then the Power-Down transition timings determine the settling
time of the DRCG. However, the MULT0, MULT1, and MULT2
control signals can also be changed during Normal mode.
When the MULT control signals are "hot swapped" in this man-
ner, the MULT transition timings determine the settling time of
the DRCG.
Table 3. Bypass and Test Mode Selection
Mode
S0
S1
S2
By Pclk
(int.)
CLK
CLK#
Normal
0
0
0
Gnd
PAClk
PAClk#
Bypass
1
0
0
PLLClk
PLLClk
PLLClk#
Test
1
1
0
RefClk
RefClk
RefClk#
Vendor Test
A
0
0
1
-
-
-
Vendor Test
B
1
0
1
-
-
-
Reserved
1
1
1
-
-
-
Output Test
(OE)
0
1
X
-
Hi-Z
RefClk#
Table 4. PWR_DWN# Mode Selection
Mode
PWR_DWN#
CLK
CLK#
Normal
1
PAClk
PAClk#
Power-Down
0
GND
GND
Table 5. Frequencies, Dividers, and Gear Ratios
Pclk
Refclk
Busclk
Synclk
A
B
M
N
Ratio
F@PD
67
33
267
67
8
1
2
2
1.0
33
100
50
300
75
6
1
8
6
1.33
12.5
100
50
400
100
8
1
4
4
1.0
25
133
67
267
67
4
1
4
2
2.0
33
133
67
400
100
6
1
8
6
1.33
16.7