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Электронный компонент: W245-30H

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Frequency Multiplying, Peak Reducing EMI Solution
W245-30
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07229 Rev. *B
Revised August 13, 2002
0
Features
Cypress PREMISTM family offering
Generates an EMI optimized clocking signal at the out-
put
Selectable output frequency range
Single 1.25%, 2.5%, 5% or 10% down or center spread
output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 20-pin SSOP (Small Shrunk Outline Pack-
age)
Key Specifications
Supply Voltages:......................................... V
DD
= 3.3V0.3V
or V
DD
= 5V10%
Frequency range: ........................... 13 MHz < F
in
< 120 MHz
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: ................................. 40/60% (worst case)
W
245
-30
20
19
18
17
1
2
3
4
X1
X2
AVDD
MW0^
REFOUT
VDD
GND
IR1*
5
6
7
14
15
16
IR2*
SSOUT
MW1*
SDATA
OR1^
8
9
10
11
12
13
VDD
MW2^
OR2*
SSON#^
GND
GND
Simplified Block Diagram
Pin Configuration
SSOP
Spread Spectrum
W245-30
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Spread Spectrum
W245-30
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
Reference Input
Input
Output
Output
X1
SCLK
SDATA
SDATA
SCLK
IIC Interface
IIC Interface
SCLK
Notes:
1.
Pins marked with ^ are internal pull-down resistors with
weak 250 k
.
2.
Pins marked with * are internal pull-up resistors with weak
80 k
.
[1, 2]
W245-30
Document #: 38-07229 Rev. *B
Page 2 of 12
Pin Description
Pin Name
Pin No.
Pin
Type
Pin Description
SSOUT
15
O
Output Modulated Frequency: Frequency modulated copy of the input clock
(SSON# asserted).
REFOUT
20
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
X1
1
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
X2
2
I
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference, this pin must be left unconnected.
SSON#
10
I
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
MW0:2
4, 11, 14
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
these pins are used to select the amount of variation and peak EMI reduction
that is desired on the output signal. MW1:Down, MW1:Up, MW2:Down (See
Table 2).
IR1:2
17, 16
I
Reference Frequency Selection: Logic level provided at this input indicates
to the internal logic what range the reference frequency is in and determines
the factor by which the device multiplies the input frequency. Refer to Table 3.
These pins have internal pull-up resistors.
OR1:2
6, 9
I
Output Frequency Selection Bits: These pins select the frequency operation
for the output. Refer to Table 1. OR2 pin have internal pull-up resistors. OR1
pin have internal pull-down resistors.
SCLK
7
I
Clock pin for SMBus circuitry.
SData
5
I/O
Data pin for SMBus Circuitry.
VDD
12, 19
P
Power Connection: Connected to 3.3V or 5V power supply.
AVDD
3
P
Analog Power Connection: Connected to 3.3V or 5V power supply.
GND
8, 13, 18
G
Ground Connection: Connect all ground pins to the common ground plane.
W245-30
Document #: 38-07229 Rev. *B
Page 3 of 12
Table 1. Frequency Configuration (Frequencies in MHz)
Table 2. Modulation Width Selection Table
Overview
The W245-30 product is one of a series of devices in the Cy-
press PREMIS family. The PREMIS family incorporates the
latest advances in PLL spread spectrum frequency synthesiz-
er techniques. By frequency modulating the output with a low
frequency carrier, peak EMI is greatly reduced. Use of this
technology allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Functional Description
The W245-30 uses a phase locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. (Note: For the W245-30 the
output frequency is nominally equal to the input frequency.)
The unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pins
MW0:2 as shown in Table 2.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
Range of Fin
Frequency
Multiplier
Settings
Output /
Input
Range of Fout
Required R
Settings
Modulation & Pow-
er Down Settings
Min.
Max.
OR2
OR1
Min.
Max.
IR2
IR1
MW2
MW1
14
30
0
1
1
14
30
0
1
Table 2
14
30
1
0
2
28
60
0
1
Table 2
14
30
1
1
4
56
120
0
1
Table 2
25
60
0
1
0.5
13
30
1
0
Table 2
25
60
1
0
1
25
60
1
0
Table 2
25
60
1
1
2
50
120
1
0
Table 2
50
120
0
1
0.25
13
30
1
1
Table 2
50
120
1
0
0.5
25
60
1
1
Table 2
50
120
1
1
1
50
120
1
1
Table 2
Reserved
0
0
N/A
N/A
N/A
As Set
As Set
1
0
Power Down Hi-Z
0
0
N/A
N/A
N/A
As Set
As Set
1
1
Power Down 0
0
0
N/A
N/A
N/A
As Set
As Set
0
0
Power Down 1
0
0
N/A
N/A
N/A
As Set
As Set
0
1
EMI Reduction
Modulation Setting
Bandwith Limit Frequencies as a% Value of Fout
MW0 = 0
MW0 = 1
MW2
MW1
Low
High
Low
High
Minimum EMI Control
0
0
98.75%
100%
99.375%
100.625
Suggested Setting
0
1
97.5%
100%
98.75
101.25%
Alternate Setting
1
0
95.0%
100%
97.5%
102.5%
Maximum EMI reduction
1
1
90.0%
100%
95%
105%
W245-30
Document #: 38-07229 Rev. *B
Page 4 of 12
Freq.
Phase
Modulating
VCO
Post
CLKOUT
Detector
Charge
Pump
Waveform
Dividers
Divider
Feedback
Divider
PLL
GND
V
DD
Q
P
Clock Input
Reference Input
(EMI suppressed)
Figure 1. Functional Block Diagram
W245-30
Document #: 38-07229 Rev. *B
Page 5 of 12
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is as described in Table 2.
Figure 3 details the Cypress spreading pattern. Cypress does
offer options with more spread and greater EMI reduction.
Contact your local Sales representative for details on these
devices.
Spread
Spectrum
Enabled
EMI Reduction
Spread
Spectrum
Non-
Frequency Span (MHz)
Down Spread
A
m
pl
itud
e
(dB
)
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
10
%
20
%
30
%
40
%
50
%
60
%
70
%
80
%
90
%
10
0%
F
R
EQUENCY
Figure 3. Typical Modulation Profile
W245-30
Document #: 38-07229 Rev. *B
Page 6 of 12
Serial Data Interface
The W245-30 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the W245-30 initial-
izes with default register settings, therefore the use of this se-
rial data interface is optional. The serial interface is write-only
(to the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W245-30 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Table 4. Byte Writing Sequence
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held low.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change un-
der normal system operation.
Spread Spectrum En-
abling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts clock output into a high impedance state.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro-
duction device testing.
No user application. Register bit must be writ-
ten as 0.
Byte Se-
quence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W245-30 to accept the bits in Data Bytes 0-6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W245-30
is 11010010. Register setting will not be made if the Slave Address is
not correct (or is for an alternate slave receiver).
2
Command Code
Don't Care
Unused by the W245-30, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
3
Byte Count
Don't Care
Unused by the W245-30, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to
Table 5
The data bits in Data Bytes 07 set internal W245-30 registers that
control device operation. The data bits are only accepted when the
Address Byte bit sequence is 11010010, as noted above. For descrip-
tion of bit control functions, refer to Table 3, Data Byte Serial Configu-
ration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
W245-30
Document #: 38-07229 Rev. *B
Page 7 of 12
Writing Data Bytes
Each bit in Data Bytes 07 control a particular device function
except for the "reserved" bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 07.
Table 5. Data Bytes 07 Serial Configuration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
Data Byte 0
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 1
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 3
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
W245-30
Document #: 38-07229 Rev. *B
Page 8 of 12
0
--
--
(Reserved)
--
--
0
Data Byte 4
7
16
IR2
MSB of Input Range Select
Refer to Table 1
0
6
17
IR1
LSB of Input Range Select
Refer to Table 1
0
5
9
OR2
MSB of Output Range Select
Refer to Table 1
0
4
6
OR1
LSB of Output Range Select
Refer to Table 1
0
3
--
--
Hardware/Software Frequency Select
Hardware
Software
0
2
--
--
Stop Function
PLL Off
PLL ON
0
1
10
SSON#
Spread Spectrum
Spread On
Spread Off
0
0
4
MW0
LSB of Modulation Width Selection
Refer to Table 2
0
Data Byte 5
7
11
MW2
MSB of Modulation Width Selection
Refer to Table 2
0
6
14
MW1
Modulation Width Selection Bit
Refer to Table 2
0
5
20
REFOUT
Output Enable
Disabled
Enabled
1
4
15
SSOUT
Output Enable
Disabled
Enabled
1
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 6
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 7
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Table 5. Data Bytes 07 Serial Configuration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
W245-30
Document #: 38-07229 Rev. *B
Page 9 of 12
Absolute Maximum Ratings
[3]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
P
D
Power Dissipation
0.5
W
DC Electrical Characteristics
: 0C < T
A
< 70C, V
DD
= 3.3V 0.3V
[4]
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
18
32
mA
t
ON
Power Up Time
First locked clock cycle after Power
Good
5
ms
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.4
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 4
-100
A
I
IH
Input High Current
Note 4
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 3.3V
15
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 3.3V
15
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
250
k
Z
OUT
Clock Output Impedance
25
Note:
3.
Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
4.
Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
W245-30
Document #: 38-07229 Rev. *B
Page 10 of 12
DC Electrical Characteristics:
0C < T
A
< 70C, V
DD
= 5V 10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
I
DD
Supply Current
30
50
mA
t
ON
Power Up Time
First locked clock cycle after
Power Good
5
ms
V
IL
Input Low Voltage
0.15V
DD
V
V
IH
Input High Voltage
0.7V
DD
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
I
IL
Input Low Current
Note 4
100
A
I
IH
Input High Current
Note 4
10
A
I
OL
Output Low Current
@ 0.4V, V
DD
= 5V
24
mA
I
OH
Output High Current
@ 2.4V, V
DD
= 5V
24
mA
C
I
Input Capacitance
7
pF
R
P
Input Pull-Up Resistor
250
k
Z
OUT
Clock Output Impedance
25
AC Electrical Characteristics:
T
A
= 0C to +70C, V
DD
= 3.3V 0.3V or 5V10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f
IN
Input Frequency
Input Clock
14
120
MHz
f
OUT
Output Frequency
Spread Off
13
120
MHz
t
R
Output Rise Time
15-pF load, 0.8V2.4V
2
5
ns
t
F
Output Fall Time
15-pF load, 2.4V0.8V
2
5
ns
t
OD
Output Duty Cycle
15-pF load
40
60
%
t
ID
Input Duty Cycle
40
60
%
t
JCYC
Jitter, Cycle-to-Cycle
250
300
ps
Ordering Information
Ordering Code
Package Type
Product Flow
W245-30H
20-Pin Plastic SSOP (209-mil)
Commercial, 0C to 70C
W245-30HT
20-Pin Plastic SSOP (209-mil)- Tape and Reel
Commercial, 0C to 70C
W245-30
Document #: 38-07229 Rev. *B
Page 11 of 12
Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimension
PREMIS is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
may be trademarks of their respective holders.
20-Lead (5.3 mm) Shrunk Small Outline Package O20
51-85077-*C
W245-30
Document #: 38-07229 Rev. *B
Page 12 of 12
Document Title: W245-30 Frequency Multiplying, Peak Reducing EMI Solution
Document Number: 38-07229
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110494
01/07/02
SZV
Change from Spec number: 38-00912 to 38-07229
*A
117404
08/19/02
RGL
Corrected the Ordering Information to match the DevMaster
*B
122693
12/27/02
RBI
Added power up requirements to maximum rating information.