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Электронный компонент: W254B

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133-MHz Spread Spectrum FTG for
Mobile Pentium III Platforms
W254B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07233 Rev. **
Revised September 27, 2001
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology (0.5% and 0.5%)
Single chip system FTG for Mobile Intel
Platforms
Two CPU outputs
Seven copies of PCI clock (one Free Running)
Seven SDRAM clock (one DCLK for Memory Hub)
Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
Three 3V66 Hublink/AGP outputs
One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
One APIC outputs
One buffered reference output
Supports frequencies up to 133 MHz
SMBus interface for programming
Power management control inputs
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU Output Skew: ...................................................... 150 ps
3V66 Output Skew: ..................................................... 175 ps
APIC, SDRAM Output Skew: ...................................... 250 ps
PCI Output Skew: ........................................................ 500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM): ......... 3.3V5%
VDDQ2 (CPU, APIC):....... 2.5V5%in Selectable Frequency
Table 1. Pin Selectable Frequency
Intel and Pentium are registered trademarks of Intel Corporation.
Input
Address
Output Frequencies
FS1 FS0 CPU SDRAM 48MHz PCI APIC
REF
3V66
0
0
66
100
48
MHz
33
MHz
14.318
MHz
66
MHz
0
1
100
100
1
0
133
133
1
1
133
100
Block Diagram
Pin Configuration
VDD_48
VDD_REF
X1
X2
GND_REF
GND_PCI
PCI_F/FS0^
PCI1/FS1^
PCI2
PCI3
PCI4
PCI5
PCI6
VDD_3V66
3V66_0
3V66_1
3V66_AGP
GND_3V66
VCH_CLK
GND_48
USB
DOT
GND_CORE
W
2
54B
REF
APIC
VDD_APIC
CPU
CPU_F
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
DCLK
VDD_SDRAM
CPU_STP#
PCI_STP#
PWR_DWN#
SCLK
SDATA
VDD_CORE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_CPU
VDD_SDRAM
VDD_REF
VDD_APIC
APIC
CPU
CPU_F
PCI_F/FS0
XTAL
PLL Ref Freq
X2
X1
REF
VDD_PCI
USB (48MHz)
VCH_CLK
OSC
VDD_CPU
SCLK
PCI1/FS1
Stop
Clock
Control
Stop
Clock
Control
PLL 1
SMBus
Logic
DOT (48MHz)
PLL2
PWR_DWN#
VDD_48
SDATA
VDD_SDRAM
SDRAM0:5
VDD_3V66
3V66_0:1
3V66_AGP
Divider
Network
PCI2:6
DCLK
CPU_STP#
PCI_STP#
3V66_1
PCI6
VDD_PCI
Note:
1.
Internal pull-down or pull-up resistors present on inputs
marked with * or ^ respectively. Design should not rely solely
on internal pull-up or pull-down resistor to set I/O pins HIGH
or LOW respectively.
W254B
Document #: 38-07233 Rev. **
Page 2 of 17
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU
CPU_F
44, 43
O
CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial input
interface. The CPU output is gated by the CLK_STOP# input.
PCI1:6,
PCI_F/FS0,
PCI1/FS1
8, 10, 11, 12, 13,
6, 7
I/O
33-MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by
the PCI_STOP# input.
Upon power up, FS0 and FS1 is configured momentarily as input latches allowing
various output frequencies to be selected. See Table 2.
APIC
47
O
APIC Output: 2.5V fixed 33.3-MHz clock. This output is synchronous to the CPU
clock.
SDRAM0:5,
DCLK
40, 39, 37, 36,
34, 33, 32
O
SDRAM Output Clocks: 3.3V outputs running at either 100 MHz or 133 MHz
depending on the setting of FS0:1 inputs. DCLK is a free-running clock.
3V66_0:1,
3V66_AGP
15, 16, 17
O
66-MHz Clock Outputs: 3.3V fixed 66-MHz clock.
USB
21
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output.
DOT
22
O
Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal.
REF
48
O
Reference Clock: 3.3V 14.318-MHz clock output.
VCH_CLK
19
O
Video Control Hub Clock Output: 3.3V selectable 48-MHz non-spread spec-
trum or 66.67-MHz spread spectrum clock output.
PWR_DWN#
28
I
Power-Down Control: 3.3V LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU_STP#
30
I
CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0
clock. Output remains in the LOW state.
PCI_STP#
29
I
PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks.
Output remains in the LOW state.
SCLK
27
I
SMBus Clock Input: Clock pin for SMBus circuitry.
SDATA
26
I/O
SMBus Data Input: Data pin for SMBus circuitry.
X1
2
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
3
O
Crystal Connection: Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
VDD_REF,
VDD_PCI,
VDD _3V66,
VDD_48,
VDD_CORE,
VDD_SDRAM,
VDD_SDRAM
1, 9, 14, 23, 25,
31, 38
P
3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM
outputs buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
VDD_APIC,
VDD_CPU
45, 46
P
2.5V Power Connection: Power for APIC and CPU output buffers. Connect to
2.5V.
GND_REF,
GND_PCI,
GND_3V66,
GND_48,
GND_CORE
GND_SDRAM,
GND_SDRAM,
GND_CPU
4, 5, 18, 20, 24,
35, 41, 42
G
Ground Connection: Connect all ground pins to the common system ground
plane.
W254B
Document #: 38-07233 Rev. **
Page 3 of 17
Overview
The W254B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel architec-
ture platform using graphics-integrated core logic.
Functional Description
I/O Pin Operation
Pins 6 and 7 are dual-purpose l/O pins. Upon power-up these
pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins then become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
"strapping" resistor is connected between
each l/O pin and ground or VDDQ3. Connection to ground
sets a latch to "0", connection to VDDQ3 sets a latch to "1".
Figure 1 shows one suggested method for strapping resistor
connection.
Upon W254B power-up, the first 2 ms of operation is used for
input logic selection. During this period, the PCI_F and PCI1
clock output buffers are three-stated, allowing the output
strapping resistor on each l/O pin to pull the pin and its asso-
ciated capacitive clock load to either a logic HIGH or logic
LOW state. At the end of the 2-ms period, the established
logic 0 or 1 condition of each l/O is pin is latched. Next the
output buffers are enabled, converting all l/O pins into operat-
ing clock outputs. The 2-ms timer starts when VDDQ3
reaches 2.0V. The input bits can only be reset by turning
VDDQ3 off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 40
(nominal), which is minimally
affected by the 10-k
strap to ground or VDDQ3. As with the
series termination resistor, the output strapping resistor
should be placed as close to the l/O pin as possible in order
to keep the interconnecting trace short. The trace from the
resistor to ground or VDDQ3 should be kept less than two
inches in length to prevent system noise coupling during input
logic sampling.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered, assum-
ing that VDDQ3 has stabilized. If VDDQ3 has not yet reached
full value, output frequency initially may be below target but
will increase to target once VDDQ3 voltage has stabilized. In
either case, a short output clock cycle may be produced from
the CPU clock outputs when the outputs are enabled.
CPU/ SDRAM Frequency Selection
CPU output frequency is selected with I/O pins 6 and 7. For
CPU/SDRAM frequency programming information refer to
Table 2. Alternatively, frequency selections are available
through the serial data interface.
Notes:
2.
Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
3.
Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Q
D
W254B
V
DD
Clock Load
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Table 2. Frequency Select Truth Table
[2]
Input Address
Output Frequencies
FS1
FS0
CPU
SDRAM
48 MHz
[3]
PCI
APIC
REF
3V66
0
0
66
100
48 MHz
33 MHz
14.318 MHz
66 MHz
0
1
100
100
1
0
133
133
1
1
133
100
W254B
Document #: 38-07233 Rev. **
Page 4 of 17
Offsets Among Clock Signal Groups
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W254B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is oper-
ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
Table 3. 66 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to 3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
2.5 ns
7.5 ns
0.0 ns
1.5-3.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 2. Group Offset Waveforms (66 Mhz CPU/100 MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
Figure 3. Group Offset Waveforms (100 MHz CPU/100 MHz SDRAM Clock)
W254B
Document #: 38-07233 Rev. **
Page 5 of 17
Table 4. 100 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to
3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
5.0 ns
5.0ns
0.0 ns
1.5-3.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz
Table 5. 133 MHz/SDRAM 100 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to 3V66
SDRAM to
3V66
3V66 to PCI
PCI to APIC
USB & DOT
Offset
0.0 ns
0.0 ns
0.0 ns
1.5-3.5 ns
0.0 ns
Async
Tolerance
500 ps
500 ps
500 ps
500 ps
1.0 ns
N/A
Figure 5. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
0 ns
40 ns
30 ns
20 ns
10 ns
CPU 133-MHz
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Cycle Repeats
APIC33-MHz