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Электронный компонент: W255

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200-MHz 24-Output Buffer for 4 DDR
or 3 SDRAM DIMMS
W255
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07255 Rev. *B
Revised April 26, 2002
Features
One input to 24-output buffer/driver
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
One additional output for feedback
SMBus interface for individual output control
Low skew outputs (< 100 ps)
Supports 266-, 333-, and 400-MHz DDR SDRAM
Dedicated pin for power management support
Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Block Diagram
SMBus
BUF_IN
SDATA
SCLOCK
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
1
2
3
4
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
SSOP
Top View
Pin Configuration
Decoding
8
5
6
7
12
9
10
11
13
14
15
16
20
17
18
19
24
21
22
23
48
47
46
45
41
44
43
42
37
40
39
38
36
35
34
33
29
32
31
30
25
28
27
26
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
FBOUT
VDD3.3_2.5
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DRR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
SDATA
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
R_DWN#
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
FBOUT
Power Down Control
SEL_DDR
Note:
1.
Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
W255
Document #: 38-07255 Rev. *B
Page 2 of 10
Pin Summary
Pin Name
Pins
Pin Description
SEL_DDR
48
Input to configure for DDR-ONLY mode or STANDARD SDRAM
mode
.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,
42, 43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,
43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM
mode.
SCLK
25
SMBus clock input
SDATA
24
SMBus data input
BUF_IN
13
Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V
input for STANDARD SDRAM mode.
FBOUT
1
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
PWR_DWN#
36
Active LOW input to enable power-down mode; all outputs will be
pulled LOW.
DDR[6:11]T
28, 30, 34, 39, 43, 45
Clock outputs. These outputs provide copies of BUF_IN.
DDR[6:11]C
27, 29, 33, 38, 42, 44
Clock outputs. These outputs provide complementary copies of
BUF_IN.
DDR[0:5]T_SDRAM
[10,0,2,4,6,8]
4, 6, 10, 15, 19, 21
Clock outputs. These outputs provide copies of BUF_IN. Voltage swing
depends on VDD3.3_2.5 power supply.
DDR[0:5]C_SDRAM
[11,1,3,5,7,9]
5, 7, 11, 16, 20, 22
Clock outputs. These outputs provide complementary copies of
BUF_IN when SEL_DDR is active. These outputs provide copies of
BUF_IN when SEL_DDR is inactive. Voltage swing depends on
VDD3.3_2.5 power supply.
VDD3.3_2.5
2, 8, 12, 17, 23
Connect to 2.5V power supply when W255 is configured for
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is
configured for standard SDRAM mode.
VDD2.5
32, 37, 41, 47
2.5V voltage supply
GND
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground
W255
Document #: 38-07255 Rev. *B
Page 3 of 10
Serial Configuration Map
The serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Reserved and unused bits should be programmed to "0."
SMBus Address for the W255 is:
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
----
Byte 6: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Default
Bit 7
Reserved, drive to 0
0
Bit 6
Reserved, drive to 0
0
Bit 5
Reserved, drive to 0
0
Bit 4
1
FBOUT
1
Bit 3
45,44
DDR11T, DDR11C
1
Bit 2
43, 42 DDR10T, DDR10C
1
Bit 1
39, 38 DDR9T, DDR9C
1
Bit 0
34, 33 DDR8T, DDR8C
1
Byte 7: Outputs Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Pin #
Description
Default
Bit 7
30, 29
DDR7T, DDR7C
1
Bit 6
28, 27
DDR6T, DDR6C
1
Bit 5
21, 22
DDR5T_SDRAM8,
DDR5C_SDRAM9
1
Bit 4
19, 20
DDR4T_SDRAM6,
DDR4C_SDRAM7
1
Bit 3
15,16
DDR3T_SDRAM4,
DDR3C_SDRAM5
1
Bit 2
10, 11
DDR2T_SDRAM2,
DDR2C_SDRAM3
1
Bit 1
6, 7
DDR1T_SDRAM0,
DDR1C_SDRAM1
1
Bit 0
4, 5
DDR0T_SDRAM10,
DDR0C_SDRAM11
1
W255
Document #: 38-07255 Rev. *B
Page 4 of 10
Maximum Ratings
Supply Voltage to Ground Potential ..................0.5 to +7.0V
DC Input Voltage (except BUF_IN) ............ 0.5V to V
DD
+0.5
Storage Temperature.................................. 65C to +150C
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD3.3
Supply Voltage
3.135
3.465
V
VDD2.5
Supply Voltage
2.375
2.625
V
T
A
Operating Temperature (Ambient Temperature)
0
70
C
C
OUT
Output Capacitance
6
pF
C
IN
Input Capacitance
5
pF
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
IL
Input LOW Voltage
For all pins except SMBus
0.8
V
V
IH
Input HIGH Voltage
2.0
V
I
IL
Input LOW Current
V
IN
= 0V
50
A
I
IH
Input HIGH Current
V
IN
= V
DD
50
A
I
OH
Output HIGH Current
V
DD
= 2.375V
V
OUT
= 1V
18
32
mA
I
OL
Output LOW Current
V
DD
= 2.375V
V
OUT
= 1.2V
26
35
mA
V
OL
Output LOW Voltage
[2]
I
OL
= 12 mA, V
DD
= 2.375V
0.6
V
V
OH
Output HIGH Voltage
[2]
I
OH
= 12 mA, V
DD
= 2.375V
1.7
V
I
DD
Supply Current
[2]
(DDR-only mode)
Unloaded outputs, 133 MHz
400
mA
I
DD
Supply Current
(DDR-only mode)
Loaded outputs, 133 MHz
500
mA
I
DDS
Supply Current
PWR_DWN# = 0
100
A
V
OUT
Output Voltage Swing
See test circuity (refer to
Figure 1)
0.7
V
DD
+0.6
V
V
OC
Output Crossing Voltage
(V
DD
/2)
0.1
V
DD
/2
(V
DD
/2)
+0.1
V
IN
DC
Input Clock Duty Cycle
48
52
%
Switching Characteristics
[3]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Operating Frequency
66
200
MHz
Duty Cycle
[2, 4]
= t
2
t
1
Measured at 1.4V for 3.3V outputs
Measured at V
DD
/2 for 2.5V outputs
IN
DC
5%
IN
DC
+5%
%
t
3
SDRAM Rising Edge Rate
[2]
Measured between 0.4V and 2.4V
1.0
2.75
V/ns
t
4
SDRAM Falling Edge Rate
[2]
Measured between 2.4V and 0.4V
1.0
2.75
V/ns
t
3d
DDR Rising Edge Rate
[2]
Measured between 20% to 80% of
output (refer to Figure 1)
0.5
1.50
V/ns
Notes:
2.
Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.
All parameters specified with loaded outputs.
4.
Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
W255
Document #: 38-07255 Rev. *B
Page 5 of 10
t
4d
DDR Falling Edge Rate
[2]
Measured between 20% to 80% of
output (refer to Figure 1)
0.5
1.50
V/ns
t
5
Output to Output Skew for DDR
[2]
All outputs equally loaded
100
ps
t
6
Output to Output Skew for
SDRAM
[2]
All outputs equally loaded
150
ps
t
7
SDRAM Buffer LH Prop. Delay
[2]
Input edge greater than 1 V/ns
5
10
ns
t
8
SDRAM Buffer HL Prop. Delay
[2]
Input edge greater than 1 V/ns
5
10
ns
Switching Characteristics
(continued)
[3]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t
1
t
2
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t
4
Output-Output Skew
t
5
OUTPUT
OUTPUT
SDRAM Buffer HH and LL Propagation Delay
t
6
INPUT
OUTPUT
t
7
1.5V
1.5V