FTG for VIA Pro-266 DDR Chipset

W311

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

July 3, 2003

1W311

Features

· Maximized EMI Suppression using Cypress's Spread

Spectrum Technology

· System frequency synthesizer for VIA Pro-2000
· Programmable clock output frequency with less than

1 MHz increment

· Integrated fail-safe Watchdog Timer for system

recovery

· Automatically switch to HW selected or SW

programmed clock frequency when Watchdog Timer
time-out

· Capable of generate system RESET after a Watchdog

Timer time-out occurs or a change in output frequency
via SMBus interface

· Support SMBus byte read/write and block read/ write

operations to simplify system BIOS development

· Vendor ID and Revision ID support
· Programmable drive strength for CPU and PCI output

clocks

· Programmable output skew between CPU, AGP and PCI

· Supports Intel® Celeron® and Pentium® III class pro-

cessor

· Three copies of CPU output
· Nine copies of PCI output
· One 48-MHz output for USB
· One 24-MHz or 48-MHz output for SIO
· Two buffered reference outputs
· Three copies of APIC output
· Supports frequencies up to 200 MHz
· SMBus interface for programming
· Power management control inputs
· Available in 48-pin SSOP

Key Specifications

CPU Cycle-to-Cycle Jitter:........................................... 250 ps
CPU to CPU Output Skew: .......................................... 175 ps
PCI Cycle to Cycle Jitter:............................................. 500 ps
PCI to PCI Output Skew: ............................................. 500 ps

Intel, Pentium, and Celeron are registered trademarks of Intel Corporation.

Block Diagram

Pin Configuration

Note:

Signals marked with `*' have internal pull-up resistors.

[1]

V D D _ R E F

R E F 0

XTA L

PLL Ref Freq

PLL 1

X 2

X 1

R E F 1 /F S 4

V D D _ P C I

Stop

Clock

C ontrol

P C I1 :8

4 8 M H z/F S 3

2 4 _ 4 8 M H z/F S 2

PLL2

÷6, ÷8,

OSC

PW R _ D W N #

V D D _ 4 8 M H z

SM Bus

SD ATA

Logic

S C L K

C P U 1 :3

R S T #

VDD_REF

GND_REF

X1
X2

VDD_48 MHz

FS3*/48 MHz

FS2*/24_48 MHz

GND_48 MHz

PCI_F

PCI1
PCI2

GND_PCI

PCI3
PCI4

VDD_PCI

PCI5
PCI6
PCI7

GND_PCI

PCI8
*FS1
*FS0

AGP0

VDD_AGP

REF0
REF1/FS4*
VDD_APIC
APIC0
APIC1
GND_APIC
APIC2
VDD_CPU
GND_CPU
CPU1
CPU2
VDD_CPU
GND_CPU
CPU3
CPU_STOP#*
PCI_STOP#*
RST#
VDD_CORE
GND_CORE
SDATA
SCLK
AGP2
AGP1
GND_AGP

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

÷2

Stop

C lock

C ontrol

P C I_ STO P #

P C I_ F

DIV

A P IC 0 :1

A G P 0:2

DIV

FS 0:1

C P U _ STO P #

V D D _C P U

V D D _ A G P

V D D _ A P IC

÷10, ÷12

W311

Pin Definitions

Pin Name

Pin No.

Pin

Type

Pin Description

RST#

(open-

drain)

System Reset Output: Open-drain system reset output.

CPU1:3

39, 38, 35

CPU Clock Output: Frequency is set by the FS0:4 input or through serial input interface.
The CPU1:3 outputs are gated by the CLK_STOP# input.

CPU_STOP#

CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3.

PCI1:8

10, 11, 13,
14, 16, 17,

18, 20

PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through serial
input interface; see Table 5 for details. PCI1:8 outputs are gated by the PCI_STOP#
input.

PCI_STOP#

PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8.

PCI_F

Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through serial
input interface; see Table 5 for details.

APIC0:2

45, 44, 42

APIC Clock Output: APIC clock outputs.

48MHz/FS3

I/O

48-MHz Output/Frequency Select 3: 48 MHz is provided in normal operation. In stan-
dard PC systems, this output can be used as the reference for the Universal Serial Bus
host controller. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 5.

24_48MHz/
FS2

I/O

24_48-MHz Output/Frequency Select 2: In standard PC systems, this output can be
used as the clock input for a Super I/O chip. The output frequency is controlled by
Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves
as a power-on strap option to determine device operating frequency as described in
Table 5.

REF1/FS4

I/O

Reference Clock Output 1/Frequency Select 4: 3.3V 14.318-MHz output clock. This
pin also serves as a power-on strap option to determine device operating frequency as
described in Table 5.

REF0

Reference Clock Output 0: 3.3V 14.318-MHz output clock.

SCLK

Clock pin for SMBus circuitry.

SDATA

I/O

Data pin for SMBus circuitry.

Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.

Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.

VDD_REF,
VDD_48MHz,
VDD_PCI,
VDD_AGP,
VDD_CORE

1, 5,15, 24,

Power Connection: Power supply for core logic, PLL circuitry, PCI outputs, reference
outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply.

VDD_CPU,
VDD_APIC

41, 46, 37

Power Connection: Power supply for APIC and CPU output buffers, connect to 2.5V.

GND_REF,
GND_48MHz,
GND_PCI,
GND_AGP,
GND_CORE,
GND_CPU,
GND_APIC

2, 8, 12, 19,

25, 30, 36,

40, 43

Ground Connections: Connect all ground pins to the common system ground plane.

W311

Serial Data Interface

The W312 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions.

Data Protocol

The clock driver serial protocol supports byte/word write,
byte/word read, block write, and block read operations from the

controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been transferred.
For byte/word write and byte read operations, system control-
ler can access individual indexed byte. The offset of the in-
dexed byte is encoded in the command code.

The definition for the command code is defined as follows:

Table 1. Command Code Definition

Bit

Descriptions

0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation

6:0

Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at `0000000'.

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits
`00000000' stands for block operation

11:18

Command Code - 8 bits
`00000000' stands for block operation

Acknowledge from slave

20:27

Byte Count - 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address - 7 bits

29:36

Data byte 0 - 8 bits

Read

Acknowledge from slave

38:45

Data byte 1 - 8 bits

30:37

Byte count from slave - 8 bits

Acknowledge from slave

Acknowledge

...

Data Byte N/Slave Acknowledge...

39:46

Data byte from slave - 8 bits

...

Data Byte N - 8 bits

Acknowledge

...

Acknowledge from slave

48:55

Data byte from slave - 8 bits

...

Stop

Acknowledge

...

Data bytes from slave/Acknowledge

...

Data byte N from slave - 8 bits

...

Not Acknowledge

...

Stop

W311

Table 3. Word Read and Word Write Protocol

Word Write Protocol

Word Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte or word operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

Acknowledge from slave

20:27

Data byte low- 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address - 7 bits

29:36

Data byte high - 8 bits

Read

Acknowledge from slave

Stop

30:37

Data byte low from slave - 8 bits

Acknowledge

39:46

Data byte high from slave - 8 bits

NOT acknowledge

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description

Start

2:8

Slave address - 7 bits

2:8

Slave address - 7 bits

Write

Acknowledge from slave

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

11:18

Command Code - 8 bits
`1xxxxxxx' stands for byte operation
bit[6:0] of the command code represents the off-
set of the byte to be accessed

Acknowledge from slave

20:27

Data byte - 8 bits

Repeat start

Acknowledge from slave

21:27

Slave address - 7 bits

Stop

Read

Acknowledge from slave

30:37

Data byte from slave - 8 bits

Not Acknowledge

Stop

W311

W311 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be writ-

ten to a "0" level.

3. All register bits labeled "Initialize to 0" must be written to

zero during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

SEL2

See Table 5

Bit 5

SEL1

See Table 5

Bit 4

SEL0

See Table 5

Bit 3

FS_Override

0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings

Bit 2

SEL4

See Table 5

Bit 1

SEL3

See Table 5

Bit 0

Reserved

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

Spread Select2

`000' = Normal (spread off)

`001' = Test Mode

`010' = Reserved

`011' = Three-Stated

`100' = 0.5%

`101' = ± 0.5%

`110' = ± 0.25%

`111' = ± 0.38%

Bit 5

Spread Select1

Bit 4

Spread Select0

Bit 3

CPU3

(Active/Inactive)

Bit 2

CPU2

(Active/Inactive)

Bit 1

CPU1

(Active/Inactive)

Bit 0

APIC2

(Active/Inactive)

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Bit 7

PCI8

(Active/Inactive)

Bit 6

PCI7

(Active/Inactive)

Bit 5

PCI6

(Active/Inactive)

Bit 4

PCI5

(Active/Inactive)

Bit 3

PCI4

(Active/Inactive)

Bit 2

PCI3

(Active/Inactive)

Bit 1

PCI2

(Active/Inactive)

W311

Bit 0

PCI1

(Active/Inactive)

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Byte 3: Control Register 3

Bit

Pin#

Name

Default

Description

Bit 7

Reserved

Bit 6

SEL_48MHz

0 = Select 24 MHz as output
1 = Select 48 MHz as output (default).

Bit 5

48MHz

(Active/Inactive)

Bit 4

24_48MHz

(Active/Inactive)

Bit 3

PCI_F

(Active/Inactive)

Bit 2

AGP2

(Active/Inactive)

Bit 1

AGP1

(Active/Inactive)

Bit 0

AGP0

(Active/Inactive)

Byte 4: Control Register 4

Bit

Pin#

Name

Default

Description

Bit 7

PCI_Skew1

PCI skew control
00 = Normal
01 = 500 ps
10 = Reserved
11 = +500 ps

Bit 6

PCI_Skew0

Bit 5

WD_TIMER4

These bits store the time-out value of the Watchdog
Timer. The scale of the timer is determine by the pre-
scaler.
The timer can support a value of 150 ms to 4.8 sec
when the pre-scalar is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches "0," it will set the
WD_TO_STATUS bit and generate Reset if
RST_EN_WD is enabled.

Bit 4

WD_TIMER3

Bit 3

WD_TIMER2

Bit 2

WD_TIMER1

Bit 1

WD_TIMER0

Bit 0

WD_PRE_SCAL
ER

0 = 150 ms
1 = 2.5 sec

Byte 5: Control Register 5

Bit

Pin#

Name

Default

Description

Bit 7

48Mhz_DRV

0 = Norm, 1 = High Drive

Bit 6

24_48MHz_DRV

0 = Norm, 1 = High Drive

Bit 5

APIC1

(Active/Inactive)

Bit 4

APIC0

(Active/Inactive)

Bit 3

Reserved

Bit 2

Reserved

Bit 1

REF1

(Active/Inactive)

Bit 0

REF0

(Active/Inactive)

W311

Byte 6: Reserved Register

Bit

Pin#

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 7: Reserved Register

Bit

Pin#

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

Reserved

Bit 5

Reserved

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

Reserved

Bit 0

Reserved

Byte 8: Vendor & Revision ID Register (Read Only)

Bit

Name

Default

Pin Description

Bit 7

Revision_ID3

Revision ID bit[3]

Bit 6

Revision_ID2

Revision ID bit[2]

Bit 5

Revision_ID1

Revision ID bit[1]

Bit 4

Revision_ID0

Revision ID bit[0]

Bit 3

Vendor_ID3

Bit[3] of Cypress Semiconductor's Vendor ID. This bit is read only.

Bit 2

Vendor_ID2

Bit[2] of Cypress Semiconductor's Vendor ID. This bit is read only.

Bit 1

Vendor _ID1

Bit[1] of Cypress Semiconductor's Vendor ID. This bit is read only.

Bit 0

Vendor _ID0

Bit[0] of Cypress Semiconductor's Vendor ID. This bit is read only.

W311

Byte 9: System RESET and Watchdog Timer Register

Bit

Name

Default

Pin Description

Bit 7

Reserved

Bit 6

PCI_DRV

PCI clock output drive strength
0 = Normal
1 = High Drive

Bit 5

Reserved

Bit 4

RST_EN_WD

This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled

Bit 3

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled

Bit 2

WD_TO_STATUS

Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)

Bit 1

WD_EN

0 = Stop and re-load Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note: W311 will generate system reset, reload a recovery frequency, and lock
itself into a recovery frequency mode after a watchdog timer time-out occurs.
Under recovery frequency mode, W311 will not respond to any attempt to
change output frequency via the SMBus control bytes. System software can
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.

Bit 0

Reserved

Byte 10: Skew Control Register

Bit

Name

Default

Description

Bit 7

CPU_Skew2

CPU skew control
000 = Normal
001 = 150 ps
010 = 300 ps
011 = 450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps

Bit 6

CPU_Skew1

Bit 5

CPU_Skew0

Bit 4

Reserved

Bit 3

Reserved

Bit 2

Reserved

Bit 1

AGP_Skew1

AGP skew control
00 = Normal
01 = 150 ps
10 = +150 ps
11 = +300 ps

Bit 0

AGP_Skew0

W311

Byte 11: Recovery Frequency N-Value Register

Bit

Name

Default

Pin Description

Bit 7

ROCV_FREQ_N7

If ROCV_FREQ_SEL is set, W311 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog Timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same fre-
quency ratio stated in the Latched FS[4:0] register. When it is set, W311will
use the frequency ratio stated in the SEL[4:0] register.
W312 supports programmable CPU frequency ranging from 50MHz to
248MHz.
W311 will change the output frequency whenever there is an update to either
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommend-
ed to use Word or Block write to update both registers within the same SMBus
bus operation.

Bit 6

ROCV_FREQ_N6

Bit 5

ROCV_FREQ_N5

Bit 4

ROCV_FREQ_N4

Bit 3

ROCV_FREQ_N3

Bit 2

ROCV_FREQ_N2

Bit 1

ROCV_FREQ_N1

Bit 0

ROCV_FREQ_N0

Byte 12: Recovery Frequency M-Value Register

Bit

Name

Default

Pin Description

Bit 7

ROCV_FREQ_SEL

ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog Timer time-out occurs. The clock generator will automatically
switch to the recovery CPU frequency based on the selection on
ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]

Bit 6

ROCV_FREQ_M6

If ROCV_FREQ_SEL is set, W311 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog Timer time-out occurs.The setting
of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and
SDRAM. When it is cleared, W311 will use the same frequency ratio stated
in the Latched FS[4:0] register. When it is set, W311 will use the frequency
ratio stated in the SEL[4:0] register.
W311 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
W311 will change the output frequency whenever there is an update to either
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommend-
ed to use Word or Block write to update both registers within the same SMBus
bus operation.

Bit 5

ROCV_FREQ_M5

Bit 4

ROCV_FREQ_M4

Bit 3

ROCV_FREQ_M3

Bit 2

ROCV_FREQ_M2

Bit 1

ROCV_FREQ_M1

Bit 0

ROCV_FREQ_M0

Byte 13: Programmable Frequency Select N-Value Register

Bit

Name

Default

Pin Description

Bit 7

CPU_FSEL_N7

If Prog_Freq_EN is set, W311 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre-
quency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W311
will use the frequency ratio stated in the SEL[4:0] register.
W311 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.

Bit 6

CPU_FSEL_N6

Bit 5

CPU_FSEL_N5

Bit 4

CPU_FSEL_N4

Bit 3

CPU_FSEL_N3

Bit 2

CPU_FSEL_N2

Bit 1

CPU_FSEL_N1

Bit 0

CPU_FSEL_N0

W311

Byte 14: Programmable Frequency Select M-Value Register

Bit

Name

Default

Description

Bit 7

Pro_Freq_EN

Programmable output frequencies enabled
0 = disabled
1 = enabled

Bit 6

CPU_FSEL_M6

If Prog_Freq_EN is set, W311 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre-
quency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same fre-
quency ratio stated in the Latched FS[4:0] register. When it is set, W311 will
use the frequency ratio stated in the SEL[4:0] register.
W311 supports programmable CPU frequency ranging from 50MHz to
248MHz.

Bit 5

CPU_FSEL_M5

Bit 4

CPU_FSEL_M4

Bit 3

CPU_FSEL_M3

Bit 2

CPU_FSEL_M2

Bit 1

CPU_FSEL_M1

Bit 0

CPU_FSEL_M0

Byte 15: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Latched FS4 input

Latched FS[4:0] inputs. These bits are read only.

Bit 6

Latched FS3 input

Bit 5

Latched FS2 input

Bit 4

Latched FS1 input

Bit 3

Latched FS0 input

Bit 2

Vendor test mode

Reserved. Write with `0'.

Bit 1

Vendor test mode

Reserved. Write with `1'

Bit 0

Vendor test mode

Reserved. Write with `1'

Byte 16: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Vendor test mode

Reserved. Write with `0'.

Bit 6

Vendor test mode

Reserved. Write with `0'.

Bit 5

Vendor test mode

Reserved. Write with `0'.

Bit 4

Vendor test mode

Reserved. Write with `0'.

Bit 3

Vendor test mode

Reserved. Write with `0'.

Bit 2

Vendor test mode

Reserved. Write with `0'.

Bit 1

Vendor test mode

Reserved. Write with `0'.

Bit 0

Vendor test mode

Reserved. Write with `0'.

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

Vendor test mode

Reserved. Write with `0'.

Bit 6

Vendor test mode

Reserved. Write with `0'.

Bit 5

Vendor test mode

Reserved. Write with `0'.

Bit 4

Vendor test mode

Reserved. Write with `0'.

Bit 3

Vendor test mode

Reserved. Write with `0'.

W311

Bit 2

Vendor test mode

Reserved. Write with `0'.

Bit 1

Vendor test mode

Reserved. Write with `0'.

Bit 0

Vendor test mode

Reserved. Write with `0'.

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

PLL Gear Con-

stants

(G)

FS4

FS3

FS2

FS1

FS0

CPU

3V66

PCI

SEL4

SEL3

SEL2

SEL1

SEL0

200.0

66.6

33.3

48.00741

190.0

76.0

38.0

48.00741

180.0

72.0

36.0

48.00741

170.0

68.0

34.0

48.00741

166.0

66.4

33.2

48.00741

160.0

64.0

32.0

48.00741

150.0

75.0

37.5

48.00741

145.0

72.5

36.3

48.00741

140.0

70.0

35.0

48.00741

136.0

68.0

34.0

48.00741

130.0

65.0

32.5

48.00741

124.0

62.0

31.0

48.00741

66.6

33.3

48.00741

100.0

66.6

33.3

48.00741

118.0

78.7

39.3

48.00741

133.3

66.6

33.3

48.00741

66.8

33.4

48.00741

100.2

66.8

33.4

48.00741

115.0

76.7

38.3

48.00741

133.6

66.8

33.4

48.00741

66.8

33.4

48.00741

100.2

66.8

33.4

48.00741

110.0

73.3

36.7

48.00741

133.6

66.8

33.4

48.00741

105.0

70.0

35.0

48.00741

90.0

60.0

30.0

48.00741

85.0

56.7

28.3

48.00741

78.0

39.0

48.00741

66.6

33.3

48.00741

100.0

66.6

33.3

48.00741

75.0

37.5

48.00741

133.3

66.6

33.3

48.00741

W311

Programmable Output Frequency, Watchdog
Timer and Recovery Output Frequency
Functional Description

The Programmable Output Frequency feature allows users to
generate any CPU output frequency from the range of 50 MHz
to 248 MHz. Cypress offers the most dynamic and the simplest
programming interface for system developers to utilize this fea-
ture in their platforms.

The Watchdog Timer and Recovery Output Frequency fea-
tures allow users to implement a recovery mechanism when
the system hangs or getting unstable. System BIOS or other
control software can enable the Watchdog timer before they
attempt to make a frequency change. If the system hangs and
a Watchdog Timer time-out occurs, a system reset will be gen-
erated and a recovery frequency will be activated.

All the related registers are summarized Table 6.

Table 6. Register Summary

Name

Description

Pro_Freq_EN

Programmable output frequencies enabled
0 = Disabled (default)
1 = Enabled

When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.

When it is enabled, the CPU output frequency will be determined by the programmed value of
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between
CPU and other frequency outputs.

FS_Override

When Pro_Freq_EN is cleared or disabled,
0 = Select operating frequency by FS input pins (default)
1 = Select operating frequency by SEL bits in SMBus control bytes

When Pro_Freq_EN is set or enabled,
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default)
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes

CPU_FSEL_N,
CPU_FSEL_M

When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load when-
ever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same SMBus bus operation.

The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When
FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins.
When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in
SMBus control bytes.

ROCV_FREQ_SEL

ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]

ROCV_FREQ_N[7:0],
ROCV_FREQ_M[6:0]

When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog
Timer time-out occurs

The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PCI. When it is
cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used.
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.

The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use word or block write to update both registers
within the same SMBus bus operation.

WD_EN

0 = Stop and reload Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.

W311

How to program CPU output frequency?

When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:

Fcpu = G * (N+3)/(M+3)

"N" and "M" are the values programmed in Programmable Fre-
quency Select N-Value Register and M-Value Register, re-
spectively.

"G" stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 5.

The ratio of (N+3) and (M+3) need to be greater than "1"
[(N+3)/(M+3) > 1].

The following table lists set of N and M values for different
frequency output ranges.This example use a fixed value for the
M-Value Register and select the CPU output frequency by
changing the value of the N-Value Register.

Table 7. Examples of N and M Value for Different CPU Frequent Range

WD_TO_STATUS

Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = Time-out occurred (READ); Clear WD_TO_STATUS (WRITE)

WD_TIMER[4:0]

These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the
pre-scaler.
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the prescaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog Timer reaches "0." it will set the WD_TO_STATUS bit.

WD_PRE_SCALER

0 = 150 ms
1 = 2.5 sec

RST_EN_WD

This bit will enable the generation of a Reset pulse when a Watchdog Timer time-out occurs.
0 = Disabled
1 = Enabled

RST_EN_FC

This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled

Table 6. Register Summary

Name

Description

Frequency Ranges

Gear Constants

Fixed Value for

M-Value Register

Range of N-Value Register

for Different CPU Frequency

50 MHz 129 MHz

48.00741

97 255

130 MHz 248 MHz

48.00741

127 245

W311

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.

Parameter

Description

Rating

Unit

, V

Voltage on Any Pin with Respect to GND

0.5 to +7.0

STG

Storage Temperature

65 to +150

°C

Ambient Temperature under Bias

55 to +125

°C

Operating Temperature

0 to +70

°C

ESD

PROT

Input ESD Protection

2 (min.)

DC Electrical Characteristics:

= 0°C to +70°C, 3.3V, V

= 3.3V±5%, 2.5V, V

= 2.5V±5%

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

3.3V Supply Current CPU1:3 = 133 MHz

[2]

150 mA

2.5V Supply Current 50 mA

Logic Inputs

Input Low Voltage

GND 0.3

0.8

Input High Voltage

2.0

+ 0.3

Input Low Current

[3]

µA

Input High Current

[3]

µA

Clock Outputs

Output Low Voltage

= 1 mA

Output High Voltage

= 1 mA

3.1

Output High Voltage

CPU1:3,
APIC0:2

= 1 mA

2.2

Output Low Current

CPU1:3

= 1.25V

PCI_F, PCI1:8

= 1.5V

20.5

139

AGP0:2

= 1.25V

140

APIC0:2 V

= 1.25V

140

REF0:1

= 1.5V

48-MHz V

= 1.5V

24-MHz V

= 1.5V

Output High Current

CPU1:3

= 1.25V

PCI_F, PCI1:8

= 1.5V

139

AGP0:2

= 1.25V

140

APIC0:1

= 1.5V

48-MHz

= 1.5V

24-MHz

= 1.5V

Notes:

All clock outputs loaded with 6" 60

transmission lines with 22-pF capacitors.

Inputs have internal pull-up resistors.

W311

AC Electrical Characteristics

= 0°C to +70°C, 3.3V, V

= 3.3V±5%, 2.5V, V

= 2.5V± 5% f

XTL

= 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.

Notes:

X1 input threshold voltage (typical) is 3.3V/2.

The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.

X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Crystal Oscillator

X1 Input Threshold Voltage

[4]

DDQ3

= 3.3V

1.65

LOAD

Load Capacitance, Imposed on
External Crystal

[5]

IN,X1

X1 Input Capacitance

[6]

Pin X2 unconnected

Pin Capacitance/Inductance

Input Pin Capacitance

Except X1 and X2

OUT

Output Pin Capacitance

Input Pin Inductance

CPU Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/

Comments

CPU = 66.6 MHz

CPU = 100 MHz

CPU = 133 MHz

Unit

Min. Typ. Max.

Min.

Typ.

Max.

Min.

Typ. Max.

Period

Measured on rising edge
at 1.25

15.5

10.5

7.5

8.0

High Time

Duration of clock cycle
above 2.0V

5.2

3.0

1.87

Low Time

Duration of clock cycle be-
low 0.4V

5.0

2.8

1.67

Output Rise
Edge Rate

Measured from 0.4V to
2.0V

V/ns

Output Fall Edge
Rate

Measured from 2.0V to
0.4V

V/ns

Duty Cycle

Measured on rising and
falling edge at 1.25V

Jitter,
Cycle-to-Cycle

Measured on rising edge
at 1.25V. Maximum differ-
ence of cycle time be-
tween two adjacent cycles.

250

Output Skew

Measured on rising edge
at 1.25V

175

Frequency
Stabilization
from Power-up
(cold start)

Assumes full supply volt-
age reached within 1 ms
from power-up. Short cy-
cles exist prior to frequen-
cy stabilization.

AC Output
Impedance

Average value during
switching transition. Used
for determining series ter-
mination value.

DC Electrical Characteristics:

= 0°C to +70°C, 3.3V, V

= 3.3V±5%, 2.5V, V

= 2.5V±5% (continued)

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

W311

APIC Clock Output (Lump Capacitance Test Load = 20 pF)

PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Period

Measured on rising edge at 1.5V

High Time

Duration of clock cycle above 2.4V

Low Time

Duration of clock cycle below 0.4V

Output Rise Edge Rate

Measured from 0.4V to 2.4V

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.

500

Output Skew

Measured on rising edge at 1.5V

500

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.

1.5

Frequency Stabilization
from Power-up (cold
start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.

AC Output Impedance

Average value during switching transition. Used for
determining series termination value.

AGP Clock Outputs, (Lump Capacitance test Load = 30 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Period

Measured on rising edge at 1.5V

High Time

Duration of clock cycle above 2.4V

5.25

Low Time

Duration of clock cycle below 0.4V

5.05

Output Rise Edge Rate

Measured from 0.4V to 2.4V

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.

500

Output Skew

Measured on rising edge at 1.5V

250

Frequency Stabilization from
Power-up (cold start)

Assumes full supply voltage reached within 1
ms from power-up. Short cycles exist prior to
frequency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Frequency generated from PCI divided by 2

PCI/2

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization from
Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

W311

Document Control# 38-01095-**

REF Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Frequency generated by crystal oscillator

14.318

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization from
Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008

MHz

Deviation from 48 MHz

(48.008 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

Min.

Typ.

Max.

Unit

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

24.004

MHz

Deviation from 24 MHz

(24.004 24)/24

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/34 = 24.004 MHz)

57/34

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

Ordering Information

Ordering Code

Package Name

Package Type

W311

48-pin SSOP (300 mils)

W311

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

48-Pin Small Shrink Outline Package (SSOP, 300 mils)

Summary of nominal dimensions in inches:

Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102

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