200-MHz Spread Spectrum Clock Synthesizer/Driver

with Differential CPU Outputs

W320-03

PRELIMINARY

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07248 Rev. **

Revised September 27, 2001

Features

Benefits

· Compliant to Intel® CK-Titan Clock Synthesizer/Driver

Specifications

Supports next generation Pentium® processors using differen-
tial clock drivers

· Multiple output clocks at different frequencies

-- Three pairs of differential CPU outputs, up to

200 MHz

-- Ten synchronous PCI clocks, three free-running

-- Six 3V66 clocks

-- Two 48-MHz clocks

-- One reference clock at 14.318 MHz

-- One VCH clock

Motherboard clock generator

-- Support Multiple CPUs and a chipset

-- Support for PCI slots and chipset

-- Supports AGP, DRCG reference and Hub Link

-- Supports USB host controller and graphic controller

-- Supports ISA slots and I/O chip

· Spread Spectrum clocking (down spread)

Enables reduction of EMI and overall system cost

· Power-down features (PCI_STOP#, CPU_STOP#

PWR_DWN#)

Enables ACPI compliant designs

· Three Select inputs (Mode select & IC Frequency Select) Supports up to four CPU clock frequencies

· OE and Test Mode support

Enables ATE and "bed of nails" testing

· 56-pin SSOP package and 56-pin TSSOP package

Widely available, standard package enables lower cost

Intel and Pentium are registered trademarks of Intel Corporation.
Direct Rambus is a trademark of Rambus, Inc.

Logic Block Diagram

SSOP & TSSOP

Top View

VDD_REF

XTAL_IN

XTAL_OUT

GND_REF

PCI0

PCI5

66BUFF2/3V66_4

GND_3V66

PCI_STOP#

GND_CPU

CPU_STOP#

PCI_F2

GND_PCI

GND_3V66

VDD_CORE

VDD_ 48 MHz

MULT0

VDD_CPU

REF

PCI_F0

PCI_F1

VDD_PCI

GND_PCI

PCI1

PCI2

PCI3

VDD_PCI

PCI4

PCI6

VDD_3V66

66BUFF0/3V66_2

66BUFF1/3V66_3

66IN/3V66_5

PWR_DWN#

3V66_0

VDD_3V66

3V66_1/VCH

GND_ 48 MHz

DOT

USB

GND_IREF

IREF

CPU#2

CPU2

VDD_CPU

CPU#1

CPU1

CPU#0

CPU0

GND_CORE

PWR_GD#

SCLK

SDATA

W32

-03

Pin Configurations

VDD_REF

CPU0:2

CPU#0:2

PCI_F0:2

XTAL

PLL Ref Freq

REF

VDD_PCI

USB (48MHz)

VCH_CLK/ 3V66_1

OSC

VDD_CPU

CPU_STOP#

SCLK

PCI0:6

PCI_STOP#

Stop

Clock

Control

Stop

Clock

Control

PLL 1

SMBus

Logic

DOT (48MHz)

PWR_DWN#

S0:2

VDD_48MHz

SDATA

VDD_3V66

3V66_0

3V66_2:4/

Divider

Network

3V66_5/ 66IN

PWR

PLL 2

PWR

66BUFF0:2

Gate

PWR_GD#

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 2 of 19

Pin Summary

Name

Pins

Description

REF

3.3V 14.318-MHz clock output

XTAL_IN

14.318-MHz crystal input

XTAL_OUT

14.318-MHz crystal input

CPU, CPU# [0:2]

44, 45, 48, 49, 51, 52

Differential CPU clock outputs

3V66_0

3.3V 66-MHz clock output

3V66_1/VCH

3.3V selectable through SMBus to be 66 MHz or 48 MHz

66IN/3V66_5

66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from
internal VCO

66BUFF [2:0] /3V66 [4:2]

21, 22, 23

66-MHz buffered outputs from 66Input or 66-MHz clocks from internal
VCO

PCI_F [0:2]

5, 6, 7,

33 MHz clocks divided down from 66Input or divided down from 3V66

PCI [0:6]

10, 11, 12, 13, 16, 17, 18

PCI clock outputs divided down from 66Input or divided down from
3V66

USB

Fixed 48-MHz clock output

DOT

Fixed 48-MHz clock output

Special 3.3V 3 level input for Mode selection

S1, S0

54, 55

3.3V LVTTL inputs for CPU frequency selection

IREF

A precision resistor is attached to this pin which is connected to the
internal current reference

MULT0

3.3V LVTTL input for selecting the current multiplier for the CPU out-
puts

PWR_DWN#

3.3V LVTTL input for Power_Down# (active LOW)

PCI_STOP#

3.3V LVTTL input for PCI_STOP# (active LOW)

CPU_STOP#

3.3V LVTTL input for CPU_STOP# (active LOW)

PWRGD#

3.3V LVTTL input is a level sensitive strobe used to determine when
S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active
LOW). Once PWRGD# is sampled LOW, the status of this output will
be ignored.

SDATA

SMBus compatible SDATA

SCLK

SMBus compatible Sclk

VDD_REF, VDD_PCI,
VDD_3V66, VDD_CPU

1, 8, 14, 19, 32, 46, 50

3.3V power supply for outputs

VDD_48 MHz

3.3V power supply for 48 MHz

VDD_CORE

3.3V power supply for PLL

GND_REF, GND_PCI,
GND_3V66, GND_IREF,
VDD_CPU

4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs

GND_CORE

Ground for PLL

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 3 of 19

Clock Enable Configuration

Function Table

[1]

CPU

(MHz)

3V66[0:1]

(MHz)

66BUFF[0:2]/

3V66[2:4]

(MHz)

66IN/3V66_5

(MHz)

PCI_F/PCI

(MHz)

REF0(MHz)

USB/DOT

(MHz)

Notes:

66 MHz

66 IN

66 MHz Input

66 IN/2

14.318 MHz

48 MHz

2, 3, 4

100 MHz

66 MHz

66 IN

66 MHz Input

66 IN/2

14.318 MHz

48 MHz

2, 3, 4

200 MHz

66 MHz

66 IN

66 MHz Input

66 IN/2

14.318 MHz

48 MHz

2, 3, 4

133 MHz

66 MHz

66 IN

66 MHz Input

66 IN/2

14.318 MHz

48 MHz

2, 3, 4

66 MHz

33 MHz

14.318 MHz

48 MHz

2, 3, 4

100 MHz

66 MHz

33 MHz

14.318 MHz

48 MHz

2, 3, 4

200 MHz

66 MHz

33 MHz

14.318 MHz

48 MHz

2, 3, 4

133 MHz

66 MHz

33 MHz

14.318 MHz

48 MHz

2, 3, 4

Mid

Hi-Z

1, 5

Mid

TCLK/2

TCLK/4

TCLK/8

TCLK

TCLK/2

6, 7, 8,

Mid

Reserved

Mid

Reserved

Swing Select Functions

Mult0

Board Target
Trace/Term Z

Reference R, IREF

/(3*Rr)

Output

Current

@ Z

Rr = 221 1%,

IREF = 5.00 mA

= 4*IREF

1.0V @ 50

Rr = 475 1%,

IREF = 2.32 mA

= 6*IREF

0.7V @ 50

Clock Driver Impedances

Impedance

Buffer Name

Range

Buffer Type

Minimum

Typical

Maximum

CPU, CPU#

Type X1

REF

3.1353.465

Type 3

PCI, 3V66, 66BUFF

3.1353.465

Type 5

USB

3.1353.465

Type 3A

DOT

3.1353.465

Type 3B

PWR_DWN# CPU_STOP#

PCI_STOP#

CPU

CPU#

3V66

66BUFF

PCI_F

PCI

USB/DOT

VCOS/

OSC

IREF*2

FLOAT

LOW

OFF

IREF*2

FLOAT

OFF

IREF*2

FLOAT

OFF

Note:

TCLK is a test clock driven in on the XTALIN input in test mode.

"Normal" mode of operation.

Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.

Frequency accuracy of 48 MHz must be +167PPM to match USB default.

Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.

TCLK is a test clock over driven on the XTAL_IN input during test mode.

Required for DC output impedance verification.

These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 4 of 19

Serial Data Interface (SMBus)

To enhance the flexibility and function of the clock synthesizer,
a two signal SMBus interface is provided according to SMBus
specification. Through the Serial Data Interface, various de-
vice functions such as individual clock output buffers, etc can
be individually enabled or disabled. W320-03 support both
block read and block write operations.

The registers associated with the Serial Data Interface initial-
ize to their default setting upon power-up, and therefore use of
this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
power management functions.

Data Protocol

The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte, (most significant bit first) with the

ability to stop after any complete byte has been transferred.
Indexed bytes are not allowed.

A block write begins with a slave address and a WRITE con-
dition. The R/W bit is used by the SMBus controller as a data
direction bit. A zero indicates a WRITE condition to the clock
device. The slave receiver address is 11010010 (D2h).

A command code of 0000 0000 (00h) and the byte count bytes
are required for any transfer. After the command code, the core
logic issues a byte count which describes number of additional
bytes required for the transfer, not including the command
code and byte count bytes. For example, if the host has 20 data
bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count byte is re-
quired to be a minimum of 1 byte and a maximum of 32 bytes
It may not be 0. Figure 1 shows an example of a block write.

A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.

Data Byte Configuration Map

Start

bit

Slave Address
1 1 0 1 0 0 1 0

R/W

0/1

Command

Code

0 0 0 0 0 0 0 0

A Byte Count =

Data Byte 0

. . .

Data Byte N-1 A Stop

bit

1 bit

7 bits

8 bits

1 bit

Figure 1. An Example of a Block Write

From Master to Slave

From Slave to Master

Data Byte 0: Control Register (0 = Enable, 1 = Disable)

Bit

Affected

Pin#

Name

Description

Type

Power On

Default

Bit 7

5, 6, 7, 10,
11, 12, 13,
16, 17, 18,
33, 35

PCI [0:6]
CPU[2:0]
3V66[1:0]

Spread Spectrum Enable
0 = Spread Off, 1 = Spread On

R/W

Bit 6

TBD

Bit 5

3V66_1/VCH

VCH Select 66 MHz/48 MHz
0 = 66 MHz, 1 = 48 MHz

R/W

Bit 4

44, 45, 48,
49, 51, 52

CPU [2:0]
CPU# [2:0]

CPU_STOP#
Reflects the current value of the external CPU_STOP# pin

N/A

Bit 3

10, 11, 12,
13, 16, 17,
18

PCI [6:0]

PCI_STOP#
(Does not affect PCI_F [2:0] pins)

R/W

N/A

Bit 2

S2
Reflects the value of the S2 pin sampled on Power-up

N/A

Bit 1

S1
Reflects the value of the S1 pin sampled on Power-up

N/A

Bit 0

S0
Reflects the value of the S1 pin sampled on Power-up

N/A

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 5 of 19

Data Byte 1

Bit

Pin#

Name

Description

Type

Power On

Default

Bit 7

N/A

CPU Mult0 Value

N/A

Bit 6

N/A

TBD

Bit 5

44, 45

CPU2
CPU2#

Allow Control of CPU2 with assertion of CPU_STOP#
0 = Not free running; 1 = Free running

R/W

Bit 4

48, 49

CPU1
CPU1#

Allow Control of CPU1 with assertion of CPU_STOP#
0 = Not free running;1 = Free running

R/W

Bit 3

51, 52

CPU0
CPU0#

Allow Control of CPU0 with assertion of CPU_STOP#
0= Not free running; 1 = Free running

R/W

Bit 2

44, 45

CPU2
CPU2#

CPU2 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 1

48, 49

CPU1
CPU1#

CPU1Output Enable
1 = Enabled; 0= Disabled

R/W

Bit 0

51, 52

CPU0
CPU0#

CPU0 Output Enable
1 = Enabled; 0 = Disabled

R/W

Data Byte 2

Bit

Pin#

Name

Pin Description

Type

Power On

Default

Bit 7

N/A

Bit 6

PCI6

PCI6 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 5

PCI5

PCI5 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 4

PCI4

PCI4 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 3

PCI3

PCI3 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 2

PCI2

PCI2 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 1

PCI1

PCI1 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 0

PCI0

PCI0 Output Enable
1 = Enabled; 0 = Disabled

R/W

Data Byte 3

Bit

Pin#

Name

Pin Description

Type

Power On

Default

Bit 7

DOT

DOT 48-MHz Output Enable

R/W

Bit 6

USB

USB 48-MHz Output Enable

R/W

Bit 5

PCI_F2

Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#

R/W

Bit 4

PCI_F1

Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#

R/W

Bit 3

PCI_F0

Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#

R/W

Bit 2

PCI_F2

PCI_F2 Output Enable

R/W

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 6 of 19

Bit 1

PCI_F1

PCI_F1Output Enable

R/W

Bit 0

PCI_F0

PCI_F0 Output Enable

R/W

Data Byte 3 (continued)

Bit

Pin#

Name

Pin Description

Type

Power On

Default

Data Byte 4

Bit

Pin#

Name

Pin Description

Type

Power On

Default

Bit 7

TBD

N/A

Bit 6

TBD

N/A

Bit 5

3V66_0

3V66_0 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 4

3V66_1/VCH

3V66_1/VCH Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 3

66IN/3V66_5

3V66_5 Output Enable
1 = Enable; 0 = Disable

NOTE: THIS BIT SHOULD BE USED WHEN PIN 24 IS
CONFIGURED AS 3V66_5 OUTPUT. DO NOT CLEAR
THIS BIT WHEN PIN 24 IS CONFIGURED AS 66IN IN-
PUT.

R/W

Bit 2

66BUFF2

66-MHz Buffered 2 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 1

66BUFF1

66-MHz Buffered 1 Output Enable
1 = Enabled; 0 = Disabled

R/W

Bit 0

66BUFF0

66-MHz Buffered 0 Output Enable
1 = Enabled; 0 = Disabled

R/W

Data Byte 5

Bit

Pin#

Name

Pin Description

Type

Power On

Default

Bit 7

N/A

Bit 6

N/A

Bit 5

66BUFF [2:0]

Tpd 66IN to 66BUFF propagation delay control

R/W

Bit 4

66BUFF [2:0]

R/W

Bit 3

DOT

DOT edge rate control

R/W

Bit 2

DOT

R/W

Bit 1

USB

USB edge rate control

R/W

Bit 0

USB

R/W

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 7 of 19

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ..................................................0.5 to +7.0V

Input Voltage .............................................. 0.5V to V

+0.5

Storage Temperature (Non-Condensing) ... 65

C to +150

Max. Soldering Temperature (10 sec) ...................... +260

Junction Temperature ............................................... +150

Package Power Dissipation............................................... 1

Static Discharge Voltage ........................................................
(per MIL-STD-883, Method 3015) ............................. >2000V

Byte 6: Vendor ID

Bit

Description

Type

Power On

Default

Bit 7

Revision Code Bit 3

Bit 6

Revision Code Bit 2

Bit 5

Revision Code Bit 1

Bit 4

Revision Code Bit 0

Bit 3

Vendor ID Bit 3

Bit 2

Vendor ID Bit 2

Bit 1

Vendor ID Bit 1

Bit 0

Vendor ID Bit 0

Operating Conditions

Over which Electrical Parameters are Guaranteed

Parameter

Description

Min.

Max.

Unit

DD_REF

, V

DD_PCI

DD_CORE

DD_3V66,

DD_CPU,

3.3V Supply Voltages

3.135

3.465

DD_48 MHz

48 MHz Supply Voltage

2.85

3.465

Operating Temperature, Ambient

Input Pin Capacitance

XTAL

XTAL Pin Capacitance

22.5

Max. Capacitive Load on
USBCLK, REF
PCICLK, 3V66

20
30

(REF)

Reference Frequency, Oscillator Nominal Value

14.318

MHz

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 8 of 19

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Except Crystal Pads. Threshold voltage for crystal pads = V

2.0

Low-level Input Voltage

Except Crystal Pads

0.8

High-level Output Voltage

USB, REF, 3V66

= 1 mA

2.4

PCI

= 1 mA

2.4

Low-level Output Voltage

USB, REF, 3V66

= 1 mA

0.4

PCI

= 1 mA

0.55

Input High Current

0 < V

< V

Input Low Current

0 < V

< V

High-level Output Current

CPU
For I

=6*IRef Configuration

Type X1, V

= 0.65V

12.9

Type X1, V

= 0.74V

14.9

REF, DOT, USB

Type 3, V

= 1.00V

Type 3, V

= 3.135V

3V66, DOT, PCI

Type 5, V

= 1.00V

Type 5, V

= 3.135V

Low-level Output Current

REF, DOT, USB

Type 3, V

= 1.95V

Type 3, V

= 0.4V

3V66, PCI

Type 5, V

=1.95 V

Type 5, V

= 0.4V

Output Leakage Current

Three-state

DD3

3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, F

CPU

= 133 MHz

360

DDPD3

3.3V Shutdown Current

VDD_CORE/VDD3.3 = 3.465V

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 9 of 19

Switching Characteristics

[9]

Over the Operating Range

Parameter

Output

Description

Test Conditions

Min.

Max.

Unit

All

Output Duty Cycle

[10]

Measured at 1.5V

USB, REF,
DOT

Falling Edge Rate

Between 2.4V and 0.4V

0.5

2.0

PCI,3V66

Falling Edge Rate

Between 2.4V and 0.4V

1.0

4.0

V/ns

3V66[0:1]

3V66-3V66 Skew

Measured at 1.5V

500

66BUFF[0:2]

66BUFF-66BUFF Skew

Measured at 1.5V

175

PCI

PCI-PCI Skew

Measured at 1.5V

500

3V66,PCI

3V66-PCI Clock Jitter

3V66 leads. Measured at 1.5V

1.5

3.5

3V66

Cycle-Cycle Clock Jitter

Measured at 1.5V t

9 =

250

USB, DOT

Cycle-Cycle Clock Jitter

Measured at 1.5V t

9 =

350

PCI

Cycle-Cycle Clock Jitter

Measured at 1.5V t

9 =

500

REF

Cycle-Cycle Clock Jitter

Measured at 1.5V t

9 =

1000

CPU 1.0V Switching Characteristics

CPU

RiseTime

Measured differential waveform from
0.35V to +0.35V

175

467

CPU

Fall Time

Measured differential waveform from
0.35V to +0.35V

175

467

CPU

CPU-CPU Skew

Measured at Crossover

150

CPU

Cycle-Cycle Clock Jitter

Measured at Crossover t

8 =

150

CPU

Rise/Fall Matching

Measured with test loads

[13]

325

CPU

High-level Output Voltage
including overshoot

Measured with test loads

[13]

0.92

1.45

CPU

Low-level Output Voltage
including undershoot

Measured with test loads

[13]

-0.2

0.35

crossover

CPU

Crossover Voltage

Measured with test loads

[13]

0.51

0.76

CPU 0.7V Switching Characteristics

CPU

RiseTime

Measured single ended waveform
from 0.175V to 0.525V

175

700

CPU

Fall Time

Measured single ended waveform
from 0.175V to 0.525V

175

700

CPU

CPU-CPU Skew

Measured at Crossover

150

CPU

Cycle-Cycle Clock Jitter

Measured at Crossover t

8 =

With all outputs running

150

CPU

Rise/Fall Matching

Measured with test loads

[11, 12]

CPU

High-level Output Voltage
including overshoot

Measured with test loads

[12]

0.85

CPU

Low-level Output Voltage
including undershoot

Measured with test loads

[12]

-0.15

crossover

CPU

Crossover Voltage

Measured with test loads

[12]

0.28

0.43

Notes:

All parameters specified with loaded outputs.

10. Duty cycle is measured at 1.5V when V

= 3.3V. When V

= 2.5V, duty cycle is measured at 1.25V.

11.

Determined as a fraction of 2*(Trp Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge.

12. The 0.7V test load is R

= 33.2

, R

= 49.9

in test circuit.

13. The 1.0V test load is shown on test circuit page.

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 14 of 19

PWRGD# Timing Diagrams

GND VRM 5/12V

PWRGD#

VID [3:0]

BSEL [1:0]

PWRGD# FROM

VRM

PWRGD# FROM

NPN

Possible glitch while Clock VCC is coming

up. Will be gone in 0.20.3 ms delay.

VCC CPU CORE

PWRGD#

VCC W320 CLOCK

0.2 0.3 ms

delay

Wait for

PWRGD#

Sample
BSELS

CLOCK STATE

State 0

State 1

State 2

S tate 3

OFF

CLOCK VCO

CLOCK OUTPUTS

Figure 2. CPU Power BEFORE Clock Power.

GEN

Figure 3. CPU Power AFTER Clock Power.

GND VRM 5/12V

PWRGD#

VID [3:0]

BSEL [1:0]

PWRGD# FROM

VRM

PWRGD# FROM

NPN

VCC CPU CORE

PWRGD#

VCC W320 CLOCK

0.2 0.3 ms

delay

Wait for

PWRGD#

Sample
BSELS

CLOCK STATE

State 0

State 1

State 2

S tate 3

OFF

CLOCK VCO

LOCK OUTPUTS

GEN

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 15 of 19

Layout Example

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42

6
7

19
20

G = VIA to GND plane layer V =VIA to respective supply plane layer

Note: Each supply plane or strip should have a ferrite bead and capacitors

1
2
3
4
5

8
9

11
12

14
15
16
17

22
23

26
27
28

40
39

31
30
29

36
35
34
33
32

+3.3V Supply

Ceramic Caps C1 = 1022 µF

FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S

0.005

VDDQ3

C5 = 0.1

C6 = 10

VDDQ3

W320-03

C2 = 0.005

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 16 of 19

Test Circuit

[15, 16]

9, 15, 20, 27, 31, 36, 41, 47

VDD_REF, VDD_PCI,

OUTPUTS

W320-03

VDD_3V66, VDD_CORE

VDD_48 MHz, VDD_CPU

Test

Nodes

CPU

Ref,USB Outputs

PCI,3V66 Outputs

30 pF

20 pF

Test Node

1, 8, 14, 26, 32, 37, 46, 50

0.7V Test Load

2pF

Ordering Information

Ordering Code

Package Type

Operating

Range

W320-03

H - 56-Pin SSOP
X- 56-Pin TSSOP

Commercial

Notes:

15. Each supply pin must have an individual decoupling capacitor.
16. All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: R

= 33

= 50

9, 15, 20, 27, 31, 36, 41, 47

VDD_REF, VDD_PCI,

OUTPUTS

W320-03

VDD_3V66, VDD_CORE

VDD_48 MHz, VDD_CPU

Test

Nodes

CPU

Ref,USB Outputs

PCI,3V66 Outputs

30 pF

20 pF

Test Node

1, 8, 14, 26, 32, 37, 46, 50

1.0V Test Load

2pF

63.4

475

1.0V Amplitude

W320-03

PRELIMINARY

Document #: 38-07248 Rev. **

Page 18 of 19

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

(continued)

56-Pin Thin Shrink Small Outline Package

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W320-03

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: W320-03