PRELIMINARY

Spread Spectrum Desktop/Notebook System

Frequency Generator

W48S111-14

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

October 28, 1999, rev. 0.7

Features

· Maximized EMI suppression using Cypress's Spread

Spectrum Technology

· Reduces measured EMI by as much as 10 dB
· I

C programmable to 133 MHz

· Two skew-controlled copies of CPU output
· SEL100/66# selects CPU frequency (100 or 66.8 MHz)
· Seven copies of PCI output (synchronous w/CPU

output)

· One copy of 14.31818-MHz IOAPIC output
· One copy of 48-MHz USB output
· Selectable 24-/48-MHz clock is determined by resistor

straps on power-up

· One high-drive output buffer that produces a copy of

the 14.318-MHz reference

· Isolated core VDD pin for noise reduction

Key Specifications

Supply Voltages:....................................... V

DDQ3

= 3.3V±5%

DDQ2

= 2.5V±5%

CPU Cycle to Cycle Jitter: .......................................... 200 ps

CPU, PCI Output Edge Rate:

.........................................

1 V/ns

CPU0:1 Output Skew: ................................................ 175 ps

PCI_F, PCI1:6 Output Skew: .......................................500 ps

CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)

REF2X/SEL48#, SCLOCK, SDATA: ............... 250-k

pull-up

Note: Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.

Table 1. Pin Selectable Frequency

SEL100/66#

CPU(0:1)

PCI

100 MHz

33.3 MHz

66.8 MHz

33.4 MHz

Pin Configuration

Block Diagram

VDDQ3

REF2X/SEL48#

VDDQ3

IOAPIC

CPU0

CPU1

PCI_F

XTAL

PLL Ref Freq

PLL 1

100/66#_SEL

VDDQ3

PCI1

PCI2

PCI3

PCI4

PCI5

48MHz

24/48MHz

PLL2

÷2/÷3

OSC

VDDQ2

PCI6

GND

VDDQ3

GND

SCLOCK

SDATA

LOGIC

GND

PCI_F

PCI1
PCI2

PCI3
PCI4

VDDQ3

PCI5
PCI6

VDDQ3

48MHz

24/48MHz

GND

REF2X/SEL48#
VDDQ3

VDDQ2
IOAPIC
VDDQ2

CPU0
CPU1

VDDQ3

GND
SDATA

SCLOCK
SEL100/66#
GND

27
26

25
24
23

22
21

20
19
18

17
16

2
3

4
5
6

7
8

9
10
11

12
13

W48S111-14

PRELIMINARYPRELIMI-

Pin Definitions

Pin Name

Pin
No.

Pin

Type

Pin Description

CPU0:1

22, 21

CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.

PCI1:6
PCI_F

5, 6, 7, 8, 10,

11, 4

PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs
run synchronously to the CPU clock. Voltage swing is set by the power connection
to VDDQ3.

IOAPIC

I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.

48MHz

48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.

24/48MHz

24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.

REF2X/SEL48#

I/O

I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to V

. A 10K

resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to V

, pin

14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.

SEL100/66# 16

Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
page 1.

SDATA

I/O

C Data Pin: Data should be presented to this input as described in the I

C section

of this data sheet. Internal 250-k

pull-up resistor.

SCLOCK

C clock Pin: The I

C data clock should be presented to this input as described in

the I

C section of this data sheet.

Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.

Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.

VDDQ3

9, 12, 20, 26

Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz,
and Reference output buffers. Connect to 3.3V supply.

VDDQ2

23, 25

Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.

GND

3, 15, 19, 28

Ground Connections: Connect all ground pins to the common system ground
plane.

W48S111-14

PRELIMINARYPRELIMI-

Functional Description

I/O Pin Operation

Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input
select pins.

An external 10-k

"strapping" resistor is connected between

the l/O pin and ground or V

. Connection to ground sets a

latch to "0," connection to V

sets a latch to "1." Figure 1 and

Figure 2 show two suggested methods for strapping resistor
connections.

Upon W48S111-14 power-up, the first 2 ms of operation is
used for input logic selection. During this period, the Refer-
ence clock output buffer is three-stated, allowing the output
strapping resistor on the l/O pin to pull the pin and its associ-
ated capacitive clock load to either a logic HIGH or LOW state.
At the end of the 2-ms period, the established logic "0" or "1"
condition of the l/O pin is then latched. Next the output buffer

is enabled, which converts the l/O pin into an operating clock
output. The 2-ms timer is started when V

reaches 2.0V. The

input bit can only be reset by turning V

off and then back on

again.

It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 40

(nominal) which is minimally affected by

the 10-k

strap to ground or V

. As with the series termina-

tion resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the intercon-
necting trace short. The trace from the resistor to ground or
V

should be kept less than two inches in length to prevent

system noise coupling during input logic sampling.

When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that V

has stabilized. If V

has not yet reached

full value, output frequency initially may be below target but will
increase to target once V

voltage has stabilized. In either

case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.

Power-on

Reset
Timer

Output Three-state

Data

Latch

Hold

W48S111-14

Clock Load

10 k

Output

Buffer

(Load Option 1)

10 k

(Load Option 0)

Output
Low

Output Strapping Resistor

Series Termination Resistor

Figure 1. Input Logic Selection Through Resistor Load Option

Power-on

Reset

Timer

Output Three-state

Data

Latch

Hold

W48S111-14

Clock Load

10 k

Output

Buffer

Output

Low

Output Strapping Resistor

Series Termination Resistor

Jumper Options

Resistor Value R

Figure 2. Input Logic Selection Through Jumper Option

W48S111-14

PRELIMINARYPRELIMI-

Serial Data Interface

The W48S111-14 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S111-14
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic

outputs of the chipset. Clock device register changes are nor-
mally made upon system initialization, if required. The inter-
face can also be used during system operation for power man-
agement functions. Table 2 summarizes the control functions
of the serial data interface.

Operation

Data is written to the W48S111-14 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 3.

Table 2. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Clock Output Disable

Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.

CPU Clock Frequency
Selection

Provides CPU/PCI frequency selections beyond the
100- and 66.8-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.

For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.

Output Three-state

Puts all clock outputs into a high-impedance state.

Production PCB testing.

Test Mode

All clock outputs toggle in relation to X1 input, inter-
nal PLL is bypassed. Refer to Table 4.

Production PCB testing.

(Reserved)

Reserved function for future device revision or pro-
duction device testing.

No user application. Register bit must be writ-
ten as 0.

Table 3. Byte Writing Sequence

Byte

Sequence

Byte Name

Bit Sequence

Byte Description

Slave Address

11010010

Commands the W48S111-14 to accept the bits in Data Bytes 36 for
internal register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the
W48S111-14 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).

Command
Code

Don't Care

Unused by the W48S111-14, therefore bit values are ignored ("don't
care"). This byte must be included in the data write sequence to maintain
proper byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.

Byte Count

Don't Care

Unused by the W48S111-14, therefore bit values are ignored ("don't
care"). This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.

Data Byte 0

Don't Care

Refer to Cypress SDRAM drivers.

Data Byte 1

Data Byte 2

Data Byte 3

Refer to Table 4

The data bits in these bytes set internal W48S111-14 registers that con-
trol device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 4, Data Byte Serial Configuration Map.

Data Byte 4

Data Byte 5

Data Byte 6

W48S111-14

PRELIMINARYPRELIMI-

Writing Data Bytes

Each bit in the data bytes control a particular device function
except for the "reserved" bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 36.

Table 5 details additional frequency selections that are avail-
able through the serial data interface.

Table 6 details the select functions for Byte 3, bits 1 and 0.

Note:

Bits 0 and 1 of Data byte 6 in Table 4 MUST be programmed as the same value.

Table 4. Data Bytes 36 Serial Configuration Map

Bit(s)

Affected Pin

Control Function

Bit Control

Default

Pin No.

Pin Name

Data Byte 3

(Reserved)

SEL_2

Refer to Table 5

SEL_1

Refer to Table 5

SEL_0

Refer to Table 5

Frequency Table
Selection

Frequency Controlled
by external SEL100/
66# pin (Table 1)

Frequency Controlled
by BYT3 SEL_(2:0)
(Table 5)

(Reserved)

Bit 1

Bit 0

Function (See Table 6 for function details)

Normal Operation

Test Mode

Spread Spectrum on

All Outputs Three-stated

Data Byte 4

(Reserved)

24/48MHz

Clock output disable

Low

Active

(Reserved)

CPU1

Clock Output Disable

Low

Active

(Reserved)

CPU0

Clock Output Disable

Low

Active

Data Byte 5

PCI_F

Clock Output Disable

Low

Active

PCI6

Clock Output Disable

Low

Active

PCI5

Clock Output Disable

Low

Active

(Reserved)

PCI4

Clock Output Disable

Low

Active

PCI3

Clock Output Disable

Low

Active

PCI2

Clock Output Disable

Low

Active

PCI1

Clock Output Disable

Low

Active

Data Byte 6

(Reserved)

IOAPIC

Clock Output Disable

Low

Active

(Reserved)

REF2X

Clock Output Disable

Low

Active

[1]

REF2X

Clock Output Disable

Low

Active

[1]

W48S111-14

PRELIMINARYPRELIMI-

Note:

CPU and PCI frequency selections are listed in Table 1 and Table 5.

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

If Spread Is On

Data Byte 3, Bit 3 = 1

CPU, SDRAM
Clocks (MHz)

PCI Clocks

(MHz)

Spread Percentage

Bit 6

SEL_2

Bit 5

SEL_1

Bit 4

SEL_0

68.5

34.25

± 0.5% Center

37.5

± 0.5% Center

83.3

41.6

± 0.5% Center

66.8

33.4

± 0.5% Center

103

34.25

± 0.5% Center

112

37.3

± 0.5% Center

133.3

44.43

± 0.5% Center

100

33.3

± 0.5% Center

Table 6. Select Function for Data Byte 3, Bits 0:1

Function

Input Conditions

Output Conditions

Data Byte 3

CPU0:1

PCI_F, PCI1:6

REF2X,

IOAPIC

48MHZ

24MHZ

Bit 1

Bit 0

Normal Operation

Note 2

14.318 MHz

48 MHz

24 MHz

Test Mode

X1/2

CPU/2, 3, or 4

X1/2

X1/4

Spread Spectrum On

±0.5%

14.318 MHz

48 MHz

24 MHz

Three-state

Hi-Z

W48S111-14

PRELIMINARYPRELIMI-

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions

above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.

Parameter

Description

Rating

Unit

, V

Voltage on any pin with respect to GND

0.5 to +7.0

STG

Storage Temperature

65 to +150

°C

Operating Temperature

0 to +70

°C

Ambient Temperature under Bias

55 to +125

°C

ESD

PROT

Input ESD Protection

2 (min.)

DC Electrical Characteristics:

= 0°C to +70°C, V

DDQ3

= 3.3V±5%, V

DDQ2

= 2.5V±5%

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

DDQ3

Combined 3.3V Supply Current

CPUCLK =100 MHz
Outputs Loaded

[3]

DDQ3

Combined 2.5V Supply Current

CPUCLK =100 MHz
Outputs Loaded

[3]

Logic Inputs

Input Low Voltage

GND

0.3

0.8

Input High Voltage

2.0

0.3

Input Low Current

[4]

µA

Input High Current

[4]

µA

Input Low Current (SEL100/66#)

µA

Input High Current (SEL100/66#)

µA

Clock Outputs

Output Low Voltage

= 1 mA

Output High Voltage

= 1 mA

3.1

Output High Voltage

CPU0:1, IOAPIC I

= 1 mA

2.2

Output Low Current

CPU0:1

= 1.25V

100

PCI_F, PCI1:6

= 1.5V

120

IOAPIC

= 1.25V

140

REF2X

= 1.5V

100

130

152

48MHz, 24MHz

= 1.5V

Output High Current

CPU0:1

= 1.25V

100

PCI_F, PCI1:6

= 1.5V

120

IOAPIC

= 1.25V

155

REF2X

= 1.5V

100

130

150

48MHz, 24MHz

= 1.5V

Notes:

All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.

W48S111-14 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level).

W48S111-14

PRELIMINARYPRELIMI-

AC Electrical Characteristics

= 0°C to +70°C, V

DDQ3

= 3.3V±5%,V

DDQ2

= 2.5V± 5%, f

XTL

= 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.

Notes:

X1 input threshold voltage (typical) is V

/2.

The W48S111-14 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.

X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

Crystal Oscillator

X1 Input Threshold Voltage

[5]

DDQ3

= 3.3V

1.65

LOAD

Load Capacitance, as seen by
External Crystal

[6]

IN,X1

X1 Input Capacitance

[7]

Pin X2 unconnected

Pin Capacitance/Inductance

Input Pin Capacitance

Except X1 and X2

OUT

Output Pin Capacitance

Input Pin Inductance

DC Electrical Characteristics:

= 0°C to +70°C, V

DDQ3

= 3.3V±5%, V

DDQ2

= 2.5V±5% (continued)

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8 MHz

CPU = 100 MHz

Unit

Min.

Typ. Max.

Min.

Typ.

Max.

Period

Measured on rising edge at 1.25V

15.5

10.5

High Time

Duration of clock cycle above 2.0V

5.2

3.0

Low Time

Duration of clock cycle below 0.4V

5.0

2.8

Output Rise Edge Rate Measured from 0.4V to 2.0V

V/ns

Output Fall Edge Rate

Measured from 2.0V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at
1.25V

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.

200

Output Skew

Measured on rising edge at 1.25V

175

Frequency Stabiliza-
tion from Power-up
(cold start)

Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.

AC Output Impedance

Average value during switching transi-
tion. Used for determining series termi-
nation value.

W48S111-14

PRELIMINARYPRELIMI-

PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

Period

Measured on rising edge at 1.5V

High Time

Duration of clock cycle above 2.4V

Low Time

Duration of clock cycle below 0.4V

Output Rise Edge Rate

Measured from 0.4V to 2.4V

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.

250

Output Skew

Measured on rising edge at 1.5V

500

CPU to PCI Clock Skew

Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.

1.5

Frequency Stabilization
from Power-up (cold
start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.

AC Output Impedance

Average value during switching transition. Used for
determining series termination value.

IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

Frequency, Actual

Frequency generated by crystal oscillator

14.31818

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.0V

V/ns

Output Fall Edge Rate

Measured from 2.0V to 0.4V

V/ns

Duty Cycle

Measured on rising and falling edge at 1.25V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.

1.5

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

REF2X Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

Frequency, Actual

Frequency generated by crystal oscillator

14.318

MHz

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization from
Power-up (cold start)

Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

W48S111-14

PRELIMINARYPRELIMI-

Document #: 38-00854

48-MHz and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Test Condition/Comments

CPU = 66.8/100 MHz

Unit

Min.

Typ.

Max.

Frequency, Actual

Determined by PLL divider ratio (see m/n below)

48.008
24.004

MHz

Deviation from 48 MHz

(48.008 48)/48

+167

ppm

m/n

PLL Ratio

(14.31818 MHz x 57/17 = 48.008 MHz)

57/17, 57/34

Output Rise Edge Rate

Measured from 0.4V to 2.4V

0.5

V/ns

Output Fall Edge Rate

Measured from 2.4V to 0.4V

0.5

V/ns

Duty Cycle

Measured on rising and falling edge at 1.5V

Frequency Stabilization
from Power-up (cold start)

Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.

AC Output Impedance

Average value during switching transition. Used
for determining series termination value.

Ordering Information

Ordering Code

Freq. Mask

Code

Package

Name

Package Type

W48S111

-04

28-pin SOIC (300 mils)

W48S111-14

PRELIMINARY

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)

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