Desktop/Notebook Frequency Generator
W48S87-72
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 4, 2000 rev. *A
Features
Maximized EMI suppression using Cypress's Spread
Spectrum technology
0.5% Spread Spectrum clocking
Equivalent to the W48S67-72 with Spread Spectrum for
Tilamook, MMO, and Deschutes processors
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318-MHz (REF0:1)
Serial data interface (SDATA, SCLOCK inputs) provides
additional CPU/PCI clock frequency selections, individ-
ual output clock disabling and other functions
MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
V
DDQ3
= 3.3V5%, V
DDQ2
= 2.5V5%
Uses external 14.318-MHz crystal
Available in 48-pin SSOP (300 mils)
10
CPU output impedance
Note:
1.
Additional frequency selections provided by serial data interface; refer to Table 5 on page 8.
Table 1. Pin Selectable Frequency
[1]
60/66_SEL
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
0
60
30
1
66.8
33.4
Block Diagram
Pin Configuration
VDDQ3
REF0
VDDQ2
IOAPIC
CPU0
CPU1
CPU2
CPU3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
PCI_F
PCI0
XTAL
PLL Ref Freq
PLL 1
60/66_SEL
MODE
X2
X1
REF1
VDDQ3
Stop
Output
Control
Stop
Output
Control
PCI1
PWR_DWN#
Power
Down
Control
PCI2
PCI3
PCI4
PCI5
48/24MHZ
48/24MHZ
PLL2
2
OSC
I/O
Control
VDDQ2
CPU_STOP#
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
60/66_SEL
SDATA
SCLOCK
VDDQ3
48/24MHZ
48/24MHZ
GND
W
4
8
S
87-
72
VDDQ3
CPU2.5#
VDDQ2
IOAPIC
PWR_DWN#
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
VDDQ3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W48S87-72
2
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:3
42, 41, 39,
38
O
CPU Outputs 0 through 3: These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI0:5
9, 11, 12,
13, 14, 16
O
PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
PCI_F
8
O
Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM0:5
36, 35, 33,
32, 30, 29
O
SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run
synchronous to the CPU clock outputs. Output voltage swing is controlled by
voltage applied to VDDQ3.
SDRAM6/
CPU_STOP#
27
I/O
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the CPU_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs
CPU0:3 are stopped LOW after completing a full clock cycle (23 CPU clock
latency). When brought HIGH, clock outputs CPU0:3 are started beginning with
a full clock cycle (23 CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM7/
PCI_STOP#
26
I/O
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has
dual functions, selectable by the MODE input pin. When MODE = 0, this pin
becomes the PCI_STOP# input. When MODE = 1, this pin becomes SDRAM
clock output 7.
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW
after completing a full clock cycle. When brought HIGH, clock outputs PCI0:5
are started beginning with a full clock cycle. Clock latency provides one PCI_F
rising edge of PCI clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
IOAPIC
45
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output
voltage swing is controlled by VDDQ2.
48/24MHz
22, 23
O
48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following
device power-up. Either or both can be changed to 24 MHz through use of the
serial data interface (Byte 0, bits 2 and 3). Output voltage swing is controlled
by voltage applied to VDDQ3
REF0:1
2, 1
O
Fixed 14.318-MHz Outputs 0 through 1: Used for various system applica-
tions. Output voltage swing is controlled by voltage applied to VDDQ3. REF0
is stronger than REF1 and should be used for driving ISA slots.
CPU_2.5#
47
I
Set to logic 0 for V
DDQ2
= 2.5V (0 to 2.5V CPU output swing).
60/66_SEL
18
I
60- or 66-MHz Input Selection: Selects power-up default CPU clock frequency
as shown in Table 1 on page 1 (also determines SDRAM and PCI clock fre-
quency selections). Can be used to change CPU clock frequency while device
is in operation if serial data port bits 02 of Byte 7 are logic 1 (default power-
up condition).
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
W48S87-72
3
PWR_DWN#
44
I
Power-Down Control: When this input is LOW, the device goes into a low-
power standby condition. All outputs are actively held LOW while in power-
down. CPU, SDRAM, and PCI clock outputs are stopped LOW after completing
a full clock cycle (24 CPU clock cycle latency). When brought HIGH, CPU,
SDRAM, and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
MODE
6
I
Mode Control: This input selects the function of device pin 26
(SDRAM7/PCI_STOP#) and pin 27 (SDRAM6/CPU_STOP#). Refer to descrip-
tion for those pins.
SDATA
19
I/O
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
SCLOCK
20
I
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDDQ3
7, 15, 21, 25
28, 34, 48
P
Power Connection: Power supply for PCI0:5, REF0:1, and 48/24MHz output
buffers. Connected to 3.3V supply.
VDDQ2
46, 40
P
Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Con-
nected to 2.5V supply.
GND
3, 10, 17,
24, 31, 37,
43
G
Ground Connection: Connect all ground pins to the common system ground
plane.
Pin Definitions
(continued)
Pin Name
Pin
No.
Pin
Type
Pin Description
W48S87-72
4
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 1.
As depicted in Figure 1, a harmonic of a modulated clock has
a much lower amplitude than that of an unmodulated signal.
The reduction in amplitude is dependent on the harmonic num-
ber and the frequency deviation or spread. The equation for
the reduction is
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2. This waveform, as discussed in "Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions" by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is 0.5% of the center frequen-
cy. Figure 2 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these devices.
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate values for bits 10 in data byte 0 of the
I
2
C data stream. Refer to Table 4 for more details.
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Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
Figure 2. Typical Modulation Profile
MAX (+.0.5%)
MIN. (0.5%)
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
FREQUENCY
W48S87-72
5
Serial Data Interface
The W48S87-72 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions. Upon power-up, the W48S87-72
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of device
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs
of the chipset. Clock device register changes are normally
made upon system initialization, if any are required. The inter-
face can also be used during system operation for power man-
agement functions. Table 2 summarizes the control functions
of the serial data interface.
Operation
Data is written to the W48S87-72 in ten bytes of eight bits
each. Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
48-/24-MHz Clock Output
Frequency Selection
48-/24-MHz clock outputs can be set to 48 MHz or
24 MHz.
Provides flexibility in Super I/O and USB de-
vice selection.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
60- and 66.6-MHz selections that are provided by
the SEL60/66 input pin. Frequency is changed in a
smooth and controlled fashion.
For alternate CPU devices, and power man-
agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro-
duction device testing.
No user application. Register bit must be writ-
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address
11010010
Commands the W48S87-72 to accept the bits in Data Bytes 07 for
internal register configuration. Since other devices may exist on the
same common serial data bus, it is necessary to have a specific slave
address for each potential receiver. The slave receiver address for the
W48S87-72 is 11010010. Register setting will not be made if the Slave
Address is not correct (or is for an alternate slave receiver).
2
Command
Code
Don't Care
Unused by the W48S87-72, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
3
Byte Count
Don't Care
Unused by the W48S87-72, therefore bit values are ignored (don't care).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 4
The data bits in Data Bytes 07 set internal W48S87-72 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 4, Data Byte Serial Configuration
Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
11
Data Byte 7
W48S87-72
6
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the "reserved" bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 07.
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Table 6 details the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 07 Serial Configuration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
Data Byte 0
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
Refer to Table 5
0
5
--
--
SEL_4
Refer to Table 5
0
4
--
--
SEL_3
Refer to Table 5
0
3
23
48/24MHZ
48-/24-MHz Clock Output Frequency Selection
24 MHz
48 MHz
0
2
22
48/24MHZ
48-/24-MHz Clock Output Frequency Selection
24 MHz
48 MHz
0
10
--
--
Bit 1
Bit 0
Function (See Table 6 for function details)
0
0
Normal Operation
0
1
Test Mode
1
0
Spread Spectrum On
1
1
All Outputs Three-stated
00
Data Byte 1
7
23
48/24MHZ
Clock Output Disable
Low
Active
1
6
22
48/24MHZ
Clock Output Disable
Low
Active
1
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
38
CPU3
Clock Output Disable
Low
Active
1
2
39
CPU2
Clock Output Disable
Low
Active
1
1
41
CPU1
Clock Output Disable
Low
Active
1
0
42
CPU0
Clock Output Disable
Low
Active
1
Data Byte 2
7
--
--
(Reserved)
--
--
0
6
8
PCI_F
Clock Output Disable
Low
Active
1
5
16
PCI5
Clock Output Disable
Low
Active
1
4
14
PCI4
Clock Output Disable
Low
Active
1
3
13
PCI3
Clock Output Disable
Low
Active
1
2
12
PCI2
Clock Output Disable
Low
Active
1
1
11
PCI1
Clock Output Disable
Low
Active
1
0
9
PCI0
Clock Output Disable
Low
Active
1
Data Byte 3
7
26
SDRAM7
Clock Output Disable
Low
Active
1
6
27
SDRAM6
Clock Output Disable
Low
Active
1
5
29
SDRAM5
Clock Output Disable
Low
Active
1
4
30
SDRAM4
Clock Output Disable
Low
Active
1
3
32
SDRAM3
Clock Output Disable
Low
Active
1
2
33
SDRAM2
Clock Output Disable
Low
Active
1
1
35
SDRAM1
Clock Output Disable
Low
Active
1
0
36
SDRAM0
Clock Output Disable
Low
Active
1
W48S87-72
7
Data Byte 4
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 5
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
45
IOAPIC
Clock Output Disable
Low
Active
1
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
1
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
Data Byte 6
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
(Reserved)
--
--
0
1
--
--
(Reserved)
--
--
0
0
--
--
(Reserved)
--
--
0
Data Byte 7
7
--
--
(Reserved)
--
--
0
6
--
--
(Reserved)
--
--
0
5
--
--
(Reserved)
--
--
0
4
--
--
(Reserved)
--
--
0
3
--
--
(Reserved)
--
--
0
2
--
--
SEL_2
Refer to Table 5
1
1
--
--
SEL_1
Refer to Table 5
1
0
--
--
SEL_0
Refer to Table 5
1
Table 4. Data Bytes 07 Serial Configuration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
W48S87-72
8
Notes:
2.
CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5.
3.
In Test Mode, the 48-/24-MHz clock outputs are:
- X1/2 if 48-MHz is selected.
- X1/4 if 24-MHz is selected.
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Date Byte 0
60/66_SEL
(Pin 18)
Date Byte 7
CPU0:3
SDRAM0:7
PCI_F
PCI0:5
Spread
Spectrum%
Bit 5
SEL_4
Bit 4
SEL_3
Bit 2
SEL_2
BIT 1
SEL_1
BIT 0
SEL_0
0
0
X
0
0
0
75.0
CPU/2
0.5
0
0
X
0
0
1
75.0
32
0.5
0
0
X
0
1
0
83.31
32
0.5
0
0
X
0
1
1
33.41
CPU/2
0.5
0
0
X
1
0
0
50.11
CPU/2
0.5
0
0
X
1
0
1
68.52
CPU/2
0.5
0
0
X
1
1
0
60.0
CPU/2
0.5
0
0
0
1
1
1
60.0
CPU/2
0.5
0
0
1
1
1
1
66.82
CPU/2
0.5
0
1
0
X
X
X
60.0
CPU/2
0.5
0
1
1
X
X
X
66.6
CPU/2
0.5
1
0
0
X
X
X
60.0
CPU/2
0.5
1
0
1
X
X
X
66.6
CPU/2
0.5
1
1
0
X
X
X
60.0
CPU/2
0.5
1
1
1
X
X
X
66.6
CPU/2
0.5
Table 6. Select Function for Data Byte 0, Bits 0:1
Function
Input Conditions
Output Conditions
Data Byte 0
CPU0:3,
SRAM0:7
PCI_F,
PCI0:5
REF0:2, IOAPIC
48/24MHZ
Bit 1
Bit 0
Normal Operation
0
0
Note 2
Note 2
14.318 MHz
48 or 24 MHz
Test Mode
0
1
X1/2
X1/4
X1
Note 3
Spread Spectrum On
1
0
Note 2
Note 2
14.318 MHz
48 or 24 MHz
Three-state
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
W48S87-72
9
How To Use the Serial Data Interface
Electrical Requirements
Figure 3 illustrates electrical characteristics for the serial inter-
face bus used with the W48S87-72. Devices send data over
the bus with an open drain logic output that can (a) pull the bus
line LOW, or (b) let the bus default to logic 1. The pull-up resis-
tors on the bus (both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs to receive
data.
Although the W48S87-72 is a receive-only device (no data
write-back capability), it does transmit an "acknowledge" data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.
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W48S87-72
10
Signaling Requirements
As shown in Figure 4, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a "start bit" as shown in Figure
5. A "stop bit" signifies that a transmission has ended.
As stated previously, the W48S87-72 sends an "acknowledge"
pulse after receiving eight data bits in each byte as shown in
Figure 6.
Sending Data to the W48S87-72
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
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W48S87-72
12
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
Description
Rating
Unit
V
DD
, V
IN
Voltage on any pin with respect to GND
0.5 to +7.0
V
T
STG
Storage Temperature
65 to +150
C
T
A
Operating Temperature
0 to +70
C
T
B
Ambient Temperature under Bias
55 to +125
C
ESD
PROT
Input ESD Protection
2 (min.)
kV
DC Electrical Characteristics:
T
A
= 0C to +70C, V
DDQ3
= 3.3V5% (3.1353.465V) f
XTL
= 14.31818 MHz, V
DDQ2
= 2.55%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
DDQ3
Supply Current (3.3V)
CPUCLK =66.8 MHz
Outputs Loaded
[4]
120
150
200
mA
I
DDQ2
Supply Current (2.5V)
CPUCLK =66.8 MHz
Outputs Loaded
[4]
50
mA
Logic Inputs
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
I
IL
Input Low Current
[5]
10
A
I
IH
Input High Current
[5]
10
A
Clock Outputs
V
OL
Output Low Voltage
I
OL
= 1 mA
50
mV
V
OH
Output High Voltage
I
OH
= 1 mA
3.1
V
V
OH
Output High Voltage (CPU, IOAPIC)
I
OH
= 1 mA
2.2
V
I
OL
Output Low Current
CPU0:3
V
OL
= 1.25V
155
mA
SDRAM0:7
V
OL
= 1.5V
100
mA
PCI_F, PCI0:5
V
OL
= 1.5V
95
mA
IOAPIC
V
OL
= 1.25V
85
mA
REF0
V
OL
= 1.5V
75
mA
REF1
V
OL
= 1.5V
60
mA
48/24MHZ
V
OL
= 1.5V
60
mA
I
OH
Output High Current
CPU0:3
V
OL
= 1.25V
125
mA
SDRAM0:7
V
OL
= 1.5V
95
mA
PCI_F, PCI0:5
V
OL
= 1.5V
100
mA
IOAPIC
V
OL
= 1.25V
80
mA
REF0
V
OL
= 1.5V
80
mA
REF1
V
OL
= 1.5V
65
mA
48/24MHZ
V
OL
= 1.5V
60
mA
Notes:
4.
All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
5.
W48S87-72 logic inputs have internal pull-up devices. (Not CMOS level.)
W48S87-72
13
Crystal Oscillator
V
TH
X1 Input Threshold Voltage
[6]
V
DD
= 3.3V
1.65
V
C
LOAD
Load Capacitance, Imposed on
External Crystal
[7]
14
pF
C
IN,X1
X1 Input Capacitance
[8]
Pin X2 unconnected
28
pF
Pin Capacitance/Inductance
C
IN
Input Pin Capacitance
Except X1 and X2
5
pF
C
OUT
Output Pin Capacitance
6
pF
L
IN
Input Pin Inductance
7
nH
Serial Input Port
V
IL
Input Low Voltage
V
DD
= 3.3V
0.4
0.3V
DD
V
V
IH
Input High Voltage
V
DD
= 3.3V
0.7V
DD
2.4
V
I
IL
Input Low Current
No internal pull-up/down
on SCLOCK
10
10
A
I
IH
Input High Current
No internal pull-up/down
on SCLOCK
10
10
A
I
OL
Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On
I
OL
= 0.3V
DD
5
10
15
mA
C
IN
Input Capacitance of SDATA and
SCLOCK
5
10
pF
C
SDATA
Total Capacitance of SDATA Bus
400
pF
C
SCLOCK
Total Capacitance of SCLOCK Bus
400
pF
Notes:
6.
X1 input threshold voltage (typical) is V
DDQ3
/2.
7.
The W48S87-72 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 14 pF; this includes typical stray capacitance of short PCB traces to crystal.
8.
X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
DC Electrical Characteristics:
(continued)
T
A
= 0C to +70C, V
DDQ3
= 3.3V5% (3.1353.465V) f
XTL
= 14.31818 MHz, V
DDQ2
= 2.55%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
W48S87-72
14
AC Electrical Characteristics
T
A
= 0C to +70C, V
DD
= V
DDQ3
= 3.3V5% (3.1353.465V) f
XTL
= 14.31818 MHz, V
DDQ2
= 2.55%
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
CPU = 60 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MH
z
t
H
High Time
Duration of clock cycle above 2.4V
5.2
6
ns
t
L
Low Time
Duration of clock cycle below 0.4V
5
5.8
ns
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.25V
45
52
55
45
52
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V.
Maximum difference of cycle time be-
tween two adjacent cycles.
250
250
ps
t
SK
Output Skew
Measured on rising edge at 1.25V
250
250
ps
f
ST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cy-
cles exist prior to frequency stabiliza-
tion.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series ter-
mination value.
10
10
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
CPU = 60 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.5V
15
16.7
ns
f
Frequency, Actual
Determined by PLL divider ratio
66.8
59.876
MHz
t
R
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.5V
45
50
55
45
50
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Max-
imum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
Output Skew
Measured on rising edge at 1.5V
100
100
ps
t
SK
CPU to SDRAM Clock
Skew
Covers all CPU/SDRAM outputs. Mea-
sured on rising edge at 1.5V.
500
500
ps
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
16
16
W48S87-72
15
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
CPU = 60 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.5V
30
33.3
ns
f
Frequency, Actual
Determined by PLL divider ratio
33.4
29.938
MHz
t
H
High Time
Duration of clock cycle above 2.4V
12
13.3
ns
t
L
Low Time
Duration of clock cycle below 0.4V
12
13.3
ns
t
R
Output Rise Edge Rate
1
4
1
4
V/ns
t
F
Output Fall Edge Rate
1
4
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at
1.5V
45
51
55
45
51
55
%
t
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maxi-
mum difference of cycle time between
two adjacent cycles.
250
250
ps
t
SK
Output Skew
Measured on rising edge at 1.5V
250
250
ps
t
O
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs. Measured
on rising edge at 1.5V. CPU leads PCI
output.
1
4
1
4
ns
f
ST
Frequency Stabiliza-
tion from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Z
o
AC Output Impedance
Average value during switching transi-
tion. Used for determining series termi-
nation value.
30
30
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
Output Rise Edge Rate
1
4
V/ns
t
F
Output Fall Edge Rate
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.25V
45
52.5
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15
W48S87-72
16
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
t
F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
50
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
16
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
t
R
Output Rise Edge Rate
0.5
2
V/ns
t
F
Output Fall Edge Rate
0.5
2
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
40
48/24MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 60/66.8 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio
(see n/m below)
48.008/24.004
MHz
f
D
Deviation from 48 MHz
(48.008 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
t
R
Output Rise Edge Rate
0.5
2
V/ns
t
F
Output Fall Edge Rate
0.5
2
V/ns
t
D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
50
55
%
f
ST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Z
o
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
40
W48S87-72
17
Document #: 38-00855-*A
Serial Input Port
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f
SCLOCK
SCLOCK Frequency
Normal Mode
0
100
kHz
t
STHD
Start Hold Time
4.0
s
t
LOW
SCLOCK Low Time
4.7
s
t
HIGH
SCLOCK High Time
4.0
s
t
DSU
Data Set-up Time
250
ns
t
DHD
Data Hold Time
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
0
ns
t
R
Rise Time, SDATA and
SCLOCK
From 0.3V
DD
to 0.7V
DD
1000
ns
t
F
Fall Time, SDATA and
SCLOCK
From 0.7V
DD
to 0.3V
DD
300
ns
t
STSU
Stop Set-up Time
4.0
s
t
SPF
Bus Free Time between
Stop and Start Condition
4.7
s
t
SP
Allowable Noise Spike
Pulse Width
50
ns
Ordering Information
Ordering Code
Freq. Mask
Code
Package
Name
Package Type
W48S87
72
H
X
48-pin SSOP (300 mils)
48-pin TSSOP
W48S87-72
18
Package Diagrams
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
W48S87-72
Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
48-Pin Thin Shrink Small Outline Package (TSSOP)
8
0
COMMON
DIMENSIONS
MIN.
MAX.
C
O
N
E
T
D
4
NOTE
VARI-
ATIONS
SEE VARIATIONS
SEE VARIATIONS
L
C
O
1
N
H
e
E
D
b1
b
A
A
O
L
Y
M
B
S
MAX.
MIN.
NOM.
4
NOM.
34389
2 OF 2
A
2
THIS TABLE IN MILLIMETERS
8/1
0.50 BSC
0.10
0.90
0.27
0.15
1.10
0.05
0.17
6.00
6.10
6.20
7.95
0.50
0.60
8.10
8.25
0.75
AA
AB
6
4
4
5
12.40
12.50
12.60
13.90
14.00
14.10
THIS TABLE IN INCHES
.555
.551
.547
.496
.492
.488
5
4
4
6
AB
AA
.030
.325
.319
.024
.020
.313
.244
.240
.236
.0433
.0197 BSC
2
A
NOM.
4
NOM.
MIN.
MAX.
S
B
M
Y
L
O
A
A
b
b1
D
E
e
H
N
1
OC
L
SEE VARIATIONS
SEE VARIATIONS
ATIONS
VARI-
NOTE
4
D
T
E
N
O
C
MAX.
MIN.
DIMENSIONS
COMMON
0
8
.004
.002
.006
.0354
8
0.25
0.12
0.50
0.37
56
48
NOM.
MIN.
MAX.
S
6
N
N
6
S
MAX.
MIN.
NOM.
48
56
02
A1
0.090
0.160
0.127
C
C1
8
0.090
0.200
0.23
0.20
0.17
C1
C
.0067
.0078
.0090
.0078
.0035
8
.0050
.0063
.0035
8
.0067
.011
.0146
.0197
.0047
.0098
0.95
0.85
.0335
.0374
R EV .
D WG. N O.
SIZE
S HE ET
SC AL E
TITLE
12
A
B
C
D
E
F
G
H
B
C
D
E
F
G
H
A
12
11
10
9
8
7
6
5
4
3
2
1
11
10
9
8
7
6
5
4
3
2
1
P AC KA G E O UTLINE , 6 .10 mm (.2 40 ") B O DY,
TSS O P, 0.50 mm L EA D P ITC H
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