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033004
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Unlimited write cycles
Low-power CMOS operation
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full
=10% V
CC
operating range (DS1249Y)
Optional
=5% V
CC
operating range
(DS1249AB)
Optional industrial temperature range of
-40
C to +85
C, designated IND
JEDEC standard 32-pin DIP package
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A17
- Address Inputs
DQ0 - DQ7
- Data In/Data Out
CE
- Chip Enable
WE
- Write Enable
OE
- Output Enable
V
CC
-
Power
(+5V)
GND
-
Ground
NC
- No Connect
DESCRIPTION
The DS1249 2048k Nonvolatile SRAMs are 2,097,152-bit, fully static, nonvolatile SRAMs organized as
262,144 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
DS1249Y/AB
2048k Nonvolatile SRAM
www.maxim-ic.com
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31
32-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
DS1249Y/AB
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READ MODE
The DS1249 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 18 address inputs
(A
0
- A
17
) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing that
CE
and
OE
access times are also satisfied. If
OE
and
CE
access times are not satisfied, then data access
must be measured from the later-occurring signal (
CE
or
OE
) and the limiting parameter is either t
CO
for
CE
or t
OE
for
OE
rather than t
ACC
.
WRITE MODE
The DS1249 executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
inputs are stable. The later-occurring falling edge of
CE
or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (t
WR
)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1249AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1249Y provides full-functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protects themselves, all inputs become "don't care," and all outputs become high
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to the RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1249AB and 4.5 volts for the
DS1249Y.
FRESHNESS SEAL
Each DS1249 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
DS1249Y/AB
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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
-0.3V to +6.0V
Operating Temperature
0C to 70C, -40C to +85C for IND parts
Storage Temperature
-40C to +70C, -40C to +85C for IND parts
Soldering Temperature
260C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (t
A
: See Note 10)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
DS1249AB Power Supply Voltage
V
CC
4.75 5.0 5.25 V
DS1249Y Power Supply Voltage
V
CC
4.5
5.0 5.5 V
Logic 1
V
IH
2.2 V
CC
V
Logic 0
V
IL
0.0 0.8 V
DC ELECTRICAL (V
CC
=5V
=
5% for DS1249AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
=
10% for DS1249Y)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Leakage Current
I
IL
-2.0 +2.0
A
I/O Leakage Current
CE
V
IH
V
CC
I
IO
-2.0 +2.0
A
Output Current @ 2.4V
I
OH
-1.0
mA
Output Current @ 0.4V
I
OL
2.0
mA
Standby Current
CE
=2.2V
I
CCS1
1.0 1.5 mA
Standby Current
CE
=V
CC
-0.5V
I
CCS2
100 150
A
Operating Current
I
CCO1
85 mA
Write Protection Voltage (DS1249AB)
V
TP
4.50 4.62 4.75
V
Write Protection Voltage (DS1249Y)
V
TP
4.25 4.37 4.5
V
CAPACITANCE (t
A
=25
C)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
C
IN
10 20 pF
Input/Output Capacitance
C
I/O
10 20 pF
DS1249Y/AB
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AC ELECTRICAL (V
CC
=5V
=
5% for DS1249AB)
CHARACTERISTICS (t
A
: See Note 10) (V
CC
=5V
=
10% for DS1249Y)
DS1249AB-70
DS1249Y-70
DS1249AB-100
DS1249Y-100
PARAMETER SYMBOL
MIN MAX MIN MAX UNITS NOTES
Read Cycle Time
t
RC
70 100 ns
Access Time
t
ACC
70 100 ns
OE
to Output Valid
t
OE
35 50 ns
CE
to Output Valid
t
CO
70 100 ns
OE
or
CE
to Output Active
t
COE
5 5 ns 5
Output High Z from Deselection
t
OD
25 35 ns 5
Output Hold from Address Change
t
OH
5 5 ns
Write Cycle Time
t
WC
70 100 ns
Write Pulse Width
t
WP
55 75 ns 3
Address Setup Time
t
AW
0 0 ns
Write Recovery Time
t
WR1
t
WR2
5
15
5
15
ns
ns
12
13
Output High Z from
WE
t
ODW
25 35 ns 5
Output Active from
WE
t
OEW
5 5 ns 5
Data Setup Time
t
DS
30 40 ns 4
Data Hold Time
t
DH1
t
DH2
0
10
0
10
ns
ns
12
13
DS1249Y/AB
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READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
DS1249Y/AB
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WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
DS1249Y/AB
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POWER-DOWN/POWER-UP TIMING (t
A
: See Note 10)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
1.5
s
11
V
CC
slew from V
TP
to 0V
t
F
150
s
V
CC
slew from 0V to V
TP
t
R
150
s
V
CC
Valid to
CE
and
WE
Inactive
t
PU
2 ms
V
CC
Valid to End of Write Protection
t
REC
125
ms
(t
A
=25
C)
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
t
DR
10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. t
DS
is measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition in Write
Cycle 1, the output buffers remain in a high-impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1249 has a built-in switch that disconnects the lithium source until the user first applies V
CC
.
The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0
C to 70
C. For industrial products (IND), this range is -40
C to
+85
C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on V
CC
.
12. t
WR1
and t
DH1
are measured from
WE
going high.
13. t
WR2
and t
DH2
are measured from
CE
going high.
14. DS1249 modules are recognized by Underwriters Laboratory (U.L.
) under file E99151.
DS1249Y/AB
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DC TEST CONDITIONS
AC TEST CONDITIONS
Outputs Open
Output Load: 100 pF + 1TTL Gate
Cycle = 200 ns for operating current
Input Pulse Levels: 0 - 3.0V
All voltages are referenced to ground
Timing Measurement Reference Levels
Input:
1.5V
Output:
1.5V
Input
pulse
Rise
and
Fall
Times:
5
ns
ORDERING INFORMATION
DS1249 TTP - SSS - III
Operating
Temperature
Range
blank: 0
to 70
IND: -40
to +85
C
Access Speed
70:
70
ns
100:
100
ns
Package Type
blank:
32-pin,
600-mil
DIP
V
CC
Tolerance
Y:
10%
AB:
5%
DS1249Y/AB NONVOLATILE SRAM, 32-PIN, 740-MIL EXTENDED MODULE
PKG 32-PIN
DIM MIN MAX
A IN.
MM
2.080
52.83
2.100
53.34
B IN.
MM
0.715
18.16
0.740
18.80
C IN.
MM
0.395
10.03
0.405
10.29
D IN.
MM
0.280
7.11
0.310
7.49
E IN.
MM
0.015
0.38
0.030
0.76
F IN.
MM
0.120
3.05
0.160
4.06
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.590
14.99
0.630
16.00
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.43
0.025
0.58
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