DS2407

Dual Addressable Switch Plus

1KBit Memory

DS2407

012099 1/31

FEATURES

Open drain PIO pins are controlled and their logic
level can be determined over 1Wire

bus for

closedloop control

Dual Channel operation (TSOC package)

PIO pin channel A sink capability of 50 mA at 0.4V with
soft turnon; channel B 8 mA at 0.4V

Maximum operating voltage of 13V at PIOA, 6.5V at
PIOB

1024 bits userprogrammable OTP EPROM

7 bytes of userprogrammable status memory to con-
trol the device

Multiple DS2407s can be identified on a common
1Wire bus and be turned on or off independently of
other devices on the bus

Unique, factorylasered and tested 64bit registra-
tion number (8bit family code + 48bit serial number
+ 8bit CRC tester) assures errorfree selection and
absolute identity because no two parts are alike

Onchip CRC16 generator allows detection of data
transfer errors

Builtin multidrop controller ensures compatibility
with other MicroLAN

products

Reduces control, address, data, programming and
power to a single data pin

Directly connects to a single port pin of a microproces-
sor and communicates at up to 16.3k bits/s

Low cost TO92 or 6pin TSOC surface mount
package

1Wire communication operates over a wide voltage
range of 2.8V to 6.0V from 40

C to +85

Supports Conditional Search with userprogram-
mable condition

bondout for optional external supply to the device

(TSOC package only)

Hidden Mode; the device will respond only to a Match
ROM command or a Conditional Search when in this
mode.

PIN ASSIGNMENT

DALLAS

DS2407

TO92

BOTTOM VIEW

1
2
3

6
5
4

TSOC PACKAGE

TOP VIEW

3.7 X 4.0 X 1.5 mm

SIDE VIEW

See Mech. Drawings

Section

PIN DESCRIPTION

TO92

TSOC

Pin 1

Ground

Pin 2

Data

Pin 3

PIOA

Pin 4

Pin 5

Pin 6

PIOB

1WIRE

DATA

PIOA

PROTOCOL

PIOB

DS2407

012099 2/31

ORDERING INFORMATION

DS2407

TO92 package

DS2407P

6pin TSOC package

DS2407T

Tape & Reel version of DS2407

DS2407V

Tape & Reel version of DS2407P

DS2407X

Chip Scale Pkg., Tape & Reel

ADDRESSABLE SWITCH

DESCRIPTION

The DS2407 Dual Addressable Switch Plus Memory is
a pair of open drain Nchannel transistors that can be
turned on or off via the 1Wire bus. Alternatively, either
open drain output can serve as a logic input that can be
monitored via the same 1Wire bus. In addition, the
device has 1024 bits of EPROM to store relevant
information such as switch function, physical location,
etc. The device is addressed by matching its individual
64bit factorylasered registration number. The 64bit
number consists of an 8bit family code, a unique 48bit
serial number, and an 8bit cyclic redundancy check.
Communication with the DS2407 follows the standard
Dallas Semiconductor 1Wire protocol and can be
accomplished with a single port pin of a microcontroller.
Multiple DS2407 devices can reside on a common
1Wire bus creating a MicroLAN. The network control-
ler circuitry is embedded within the chip including a
search algorithm to determine the identity of each
DS2407 on the network. The open drain outputs (PIO
pins) for each DS2407 on the MicroLAN can be inde-
pendently switched on or off whether there is one or
many devices sharing the same 1Wire bus. The logic
level of the PIO pins for each device on the MicroLAN
can also be individually sensed and reported to the bus
master. The device also supports a Conditional Search
command to identify and access devices that qualify for
certain userspecified conditions. Qualification may be
the status of a PIOpin, the state of the output transistor
or a latched activity flag.

OVERVIEW

The DS2407 Dual Addressable Switch Plus Memory
provides a means for assigning an electronically read-
able identification to a particular node or location with
additional control capability provided by two opendrain

Nchannel MOSFETs that can be remotely switched
and sensed via communication over the 1Wire bus
(Figure 1). The DS2407 contains a factorylasered reg-
istration number that includes a unique 48bit serial
number, an 8bit CRC, and an 8bit family code (12h).
The 64bit ROM portion of the DS2407 not only creates
an absolutely unique electronic identification for the
device itself but also is a means to locate and obtain or
change the state of the switches that are associated
with the 64bit ROM.

The device derives its power entirely from the 1Wire
bus by storing energy on an internal capacitor during
periods of time when the signal line is high and contin-
ues to operate off of this "parasite" power source during
the low times of the 1Wire line until it returns high to
replenish the parasite (capacitor) supply. For applica-
tions in feedernetworks where the lowtimes of the
1Wire line may be very long, the V

pin may be con-

nected to an external voltage supply to operate the
device.

The DS2407 uses the standard Dallas Semiconductor
1Wire protocol for data transfers (Figure 2), with all
data being read and written least significant bit first.
Communication to and from the DS2407 requires a
single bidirectional line that is typically a port pin of a
microcontroller. The 1Wire bus master (microcontrol-
ler) must first issue one of five ROM function com-
mands: 1) Read ROM, 2) Match ROM, 3) Search ROM,
4) Skip ROM, or 5) Conditional Search ROM. These
commands operate on the 64bit lasered ROM portion
of each device and can singulate a specific device if
many are present on the 1Wire line as well as indicate
to the bus master how many and what type of each
device is present. After a ROM function command is
successfully executed, the opendrain outputs can be
switched or sensed, or the contents of the memory can
be read or written via the 1Wire bus. Writing the 1024
bits of data memory or writing to the EPROM sections of
the status memory requires a 12V programming pulse.
When programming the DS2407, only EPROMbased
devices are allowed to be present on the 1Wire line.

DS2407

012099 3/31

64BIT LASERED ROM

Each DS2407 contains a unique ROM code that is 64
bits long. The first eight bits are a 1Wire family code.
The next 48 bits are a unique serial number. The last
eight bits are a CRC of the first 56 bits. (See Figure 3.)
The 1Wire CRC of the lasered ROM is generated using
the polynomial X

+ X

+ 1. Additional information

about the Dallas Semiconductor 1Wire Cyclic Redun-
dancy Check is available in the Book of DS19xx
iButton Standards. The 64bit ROM and ROM Function
Control section allow the DS2407 to operate as a
1Wire device and follow the 1Wire protocol detailed in
the section "1Wire Bus System". The functions
required to read and write the data and status memory
of the DS2407 and to access the switches are not
accessible until the ROM function protocol has been
satisfied. This protocol is described in the ROM func-
tions flow chart (Figure 12). The 1Wire bus master
must first provide one of the five ROM function com-
mands. After a ROM function sequence has been suc-
cessfully executed, the bus master may then provide
any one of the memory function commands specific to
the DS2407 (Figure 6).

MEMORY

The DS2407 contains two memory sections, Data
Memory and Status Memory. The data memory consists
of 1024 bits of onetime programmable EPROM orga-
nized as 4 pages of 32 bytes each. The size of the
device's status memory is 8 bytes. The first seven bytes
of status memory (addresses 0 to 6) are also realized as
EPROM. The eighth byte (address 7) consists of SRAM
cells which shadow the contents of address 6 each time
the device powers up. The complete memory map is
shown in Figure 4. The 8bit scratchpad is an additional
register that acts as a buffer when writing the memory.
Data is first written to the scratchpad and then verified
by reading a 16bit CRC from the DS2407 that confirms
proper receipt of the data and address. If the buffer con-
tents are correct, a programming pulse should be
applied and the byte of data will be written into the
selected address in memory. This process insures data
integrity when programming the memory. The details for
reading and programming the EPROM portions of the
DS2407 are given in the Memory Function Commands
section.

DS2407

012099 6/31

DS2407 MEMORY MAP Figure 4

32BYTE FINAL STORAGE EPROM

PAGE 0

PAGE 1

8BIT

8 BYTES
STATUS

SCRATCHPAD

STARTING

ADDRESS

0000H

0020H

0040H

0060H

1K BIT

EPROM

PAGE 2

PAGE 3

MEMORY

VALID DEVICE

SETTINGS (SRAM)

POWERON

DEFAULT SETTINGS

FACTORY

BYTE

REDIRECITON

BYTES

BIT MAP OF

USED PAGES

WRITEPROTECT BITS

DATA MEMORY

32BYTE FINAL STORAGE EPROM

DS2407 STATUS MEMORY MAP Figure 5

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0 (EPROM)

BM 3

BM 2

BM 1

BM 0

WP 3

WP 2

WP 1

WP 0

1 (EPROM)

Redir. 0

2 (EPROM)

Redir. 1

3 (EPROM)

Redir. 2

4 (EPROM)

Redir. 3

5 (EPROM)

EPROM factory byte

6 (EPROM

PwrOn

Status

PIOB

PwrOn

Status

PIOA

PwrOn

Status

CSS4

PwrOn

Status

CSS3

PwrOn

Status

CSS2

PwrOn

Status

CSS1

PwrOn

Status

CSS0

7 (SRAM)

Supply

Indication

(read

only)

PIOB

Channel

FlipFlop

PIOA

Channel

FlipFlop

CSS4

Channel

Select

CSS3

Channel

Select

CSS2

Source

Select

CSS1

Source

Select

CSS0

Polarity

DS2407

012099 7/31

STATUS MEMORY

The Status Memory can be read or written to indicate
various conditions to the software interrogating the
DS2407. These conditions include special features for
the data memory, definition of the poweron default and
actual settings for the Conditional Search as well as the
channel flipflops and the external power supply indica-
tion. How these functions are assigned to the bits of the
Status Memory is detailed in Figure 5. The channel flip
flops and power supply indication are also included in
the Channel Info Byte of the Channel Access command
protocol (see Figure 6).

The first four bits of the Status Memory (address 0, bits 0
to 3) contain the Write Protect Page bits which inhibit
programming of the corresponding page in the 1024bit
data memory area if the appropriate write protection bit
is programmed. Once a bit has been programmed in the
Write Protect Page section of the Status Memory, the
entire 32 byte page that corresponds to that bit can no
longer be altered but may still be read. The remaining 4
bits of Status Memory location 0 are reserved for use by
the iButton operating software TMEX. Their purpose is
to indicate which memory pages are already in use.
Originally, all of these bits are unprogrammed, indicat-
ing that the device does not contain any data. As soon
as data is written to any page of the device under control
of TMEX, the bit inside this bitmap corresponding to that
page will be programmed to 0, marking this page as
used. These bits are application flags only and have no
impact on the internal logic of the DS2407.

The next four bytes of the Status Memory (addresses 1
to 4) contain the Page Address Redirection Bytes which
indicate if one or more of the pages of data in the
1024bits EPROM memory section have been invali-
dated by software and redirected to the page address
contained in the appropriate redirection byte. The hard-
ware of the DS2407 makes no decisions based on the
contents of the Page Address Redirection Bytes. Since
with EPROM technology bits can only be changed from
a logical 1 to a logical 0 by programming, it is not pos-
sible to simply rewrite a page if the data requires chang-
ing or updating. But with space permitting, an entire

page of data can be redirected to another page within
the DS2407. Under TMEX, a page is redirected by writ-
ing the one's complement of the new page address into
the Page Address Redirection Byte that corresponds to
the original (replaced) page. This architecture allows
the user's software to make a "data patch" to the
EPROM by indicating that a particular page or pages
should be replaced with those indicated in the Page
Address Redirection Bytes.

Under TMEX, if a Page Address Redirection Byte has a
FFh value, the data in the main memory that corre-
sponds to that page is valid. If a Page Address Redirec-
tion Byte has some other hex value than FFh, the data in
the page corresponding to that redirection byte is
invalid. According to the TMEX definitions, the valid
data will now be found at the one's complement of the
page address indicated by the hex value stored in the
associated Page Address Redirection Byte. A value of
FDh in the redirection byte for page 1, for example,
would indicate that the updated data is now in page 2.
Since the data memory consists of four pages only, the 6
most significant bits of the redirection bytes cannot be
programmed to zeros.

Status Memory location 5 is programmed to 00h at the
factory. Status Memory location 6 contains the pow-
eron default settings for the Conditional Search Select
(CSS0 to CSS4, bits 0 to 4) and the PIO channels. The
poweron settings become valid as they are internally
transferred by the device into Status Memory location 7
after the device has powered up and the bus master
sends a ROM Function Command byte for the first time.
The codes for the Conditional Search Settings are
detailed with the description of the Conditional Search
command later in this data sheet. If both CSS1 and
CSS2 in Status Memory Location 7 are set to zero, the
DS2407 will enter a "Hidden Mode" where it will keep its
status but only responds to Match ROM and Conditional
Search. To respond to Conditional Search the polarity
(CSS0) needs to be 1. The "Hidden Mode" can be ended
either by a poweron reset or by matching the device's
registration number and setting CSS1 or CSS2 to 1.

DS2407

012099 8/31

The output transistors of both channels are controlled
by their channel flipflops. These flipflops are accessi-
ble through bit locations 5 and 6 of Status Memory
address 7 as well as through the Channel Access com-
mand. Setting a channel flipflop to 0 will make the
associated PIOtransistor conducting or on, setting the
flipflop to 1 will switch the transistor off. When powering
up, the output transistors of both channels are noncon-
ducting or off. They may change their status as the
userprogrammed poweron status is transferred into
Status Memory location 7. Bit 7 of Status Memory Loca-
tion 7 indicates if the DS2407 is connected to an exter-
nal power supply. Without external supply this read
only bit will be 0. If the voltage applied to the V

pin is

high enough to keep the device powered up, this bit will
be 1.

The Status Memory is programmed similarly to the data
memory. Details for reading and programming the sta-
tus memory portion of the DS2407 are given in the
Memory Function Commands section.

MEMORY FUNCTION COMMANDS

The "Memory Function Flow Chart" (Figure 6) describes
the protocols necessary for accessing the various data
fields and PIO channels within the DS2407. The
Memory Function Control section, 8bit scratchpad,
and the Program Voltage Detect circuit combine to inter-
pret the commands issued by the bus master and create
the correct control signals within the device. A three
byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation
and two address bytes to determine the specific starting
byte location within a data field or to supply and
exchange setup and status data when accessing the
PIO channels. The command byte indicates if the
device is to be read or written or if the PIO channels are
to be accessed. Writing data involves not only issuing
the correct command sequence but also providing a
12volt programming voltage at the appropriate times.
To execute a write sequence, a byte of data is first
loaded into the scratchpad and then programmed into
the selected address. Write sequences always occur a
byte at a time. To execute a read sequence, the starting
address is issued by the bus master and data is read

from the part beginning at that initial location and contin-
uing to the end of the selected data field or until a reset
sequence is issued. All bits transferred to the DS2407
and received back by the bus master are sent least sig-
nificant bit first.

READ MEMORY [F0h]

The Read Memory command is used to read data from
the 1024bit EPROM data memory field. The bus mas-
ter follows the command byte with a twobyte address
(TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting
byte location within the data field. Since the data
memory contains 128 bytes, T15:T8 and T7 should all
be zero. With every subsequent read data time slot the
bus master receives data from the DS2407 starting at
the initial address and continuing until the end of the
1024bits data field is reached or until a Reset Pulse is
issued. If reading occurs through the end of memory
space, the bus master may issue sixteen additional read
time slots and the DS2407 will respond with a 16bit
CRC of the command, address bytes and all data bytes
read from the initial starting byte through the last byte of
memory. This CRC is the result of clearing the CRC gen-
erator and then shifting in the command byte followed
by the two address bytes and the data bytes beginning
at the first addressed memory location and continuing
through to the last byte of the EPROM data memory.
After the CRC is received by the bus master, any subse-
quent read time slots will appear as logical 1s until a
Reset Pulse is issued. Any reads ended by a Reset
Pulse prior to reaching the end of memory will not have
the 16bit CRC available.

Typically the software controlling the device should
store a 16bit CRC with each page of data to insure
rapid, errorfree data transfers that eliminate having to
read a page multiple times to determine if the received
data is correct or not. (See Book of DS19xx iButton
Standards, Chapter 7 for the recommended file struc-
ture to be used with the 1Wire environment). If CRC
values are imbedded within the data it is unnecessary to
read the endofmemory CRC. The Read Memory
command can be ended at any point by issuing a Reset
Pulse.

DS2407

012099 9/31

EXTENDED READ MEMORY [A5h]

The Extended Read Memory command supports page
redirection when reading data from the 1024bit
EPROM data field. One major difference between the
Extended Read Memory and the basic Read Memory
command is that the bus master receives the Redirec-
tion Byte (see description of Status Memory) first before
investing time in reading data from the addressed
memory location. This allows the bus master to quickly
decide whether to continue and access the data at the
selected starting page or to terminate and restart the
reading process at the redirected page address.

In addition to page redirection, the Extended Read
Memory command also supports "bitoriented" applica-
tions where the user cannot store a 16bit CRC with the
data itself. With bitoriented applications the EPROM
information may change over time within a page bound-
ary making it impossible to include an accompanying
CRC that will always be valid. Therefore, the Extended
Read Memory command concludes each page with the
DS2407 generating and supplying a 16bit CRC that is
based on and therefore always consistent with the cur-
rent data stored in each page of the 1024bit EPROM
data field.

After having sent the command code of the Extended
Read Memory command, the bus master sends a two
byte address (TA1=(T7:T0), TA2=(T15:T8)) that indi-
cates a starting byte location within the data field. By
sending eight read data time slots, the master receives
the Redirection Byte associated with the page given by
the starting address. With the next sixteen read data
time slots, the bus master receives a 16bit CRC of the
command byte, address bytes and the Redirection
Byte. This CRC is computed by the DS2407 and read
back by the bus master to check if the command word,
starting address and Redirection Byte were received
correctly.

If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, the bus master issues read time slots and receives
data from the DS2407 starting at the initial address and
continuing until the end of a 32byte page is reached. At
that point the bus master will send sixteen additional
read time slots and receive a 16bit CRC that is the

result of shifting into the CRC generator all of the data
bytes from the initial starting byte to the last byte of the
current page.

With the next 24 read data time slots the master will
receive the Redirection Byte of the next page followed
by a 16bit CRC of the Redirection Byte. After this, data
is again read from the 1024bits EPROM data field
starting at the beginning of the new page. This
sequence will continue until the final page and its
accompanying CRC are read by the bus master.

The Extended Read Memory command provides a
16bit CRC at two locations within the transaction flow
chart: 1) after the Redirection Byte and 2) at the end of
each memory page. The CRC at the end of the memory
page is always the result of clearing the CRC generator
and shifting in the data bytes beginning at the first
addressed memory location of the EPROM data page
until the last byte of this page. With the initial pass
through the Extended Read Memory flow chart the
16bit CRC value after the Redirection Byte is the result
of shifting the command byte into the cleared CRC gen-
erator, followed by the two address bytes and the
Redirection Byte. Subsequent passes through the
Extended Read Memory flow chart will generate a
16bit CRC that is the result of clearing the CRC gener-
ator and then shifting in the Redirection Byte only. After
the 16bit CRC of the last page is read, the bus master
will receive logical 1s from the DS2407 until a Reset
Pulse is issued. The Extended Read Memory command
sequence can be ended at any point by issuing a Reset
Pulse.

WRITING EPROM MEMORY

The DS2407 has two independent EPROM memory
fields, Data Memory and Status Memory. The function
flow for writing either field is almost identical. After the
appropriate write command has been issued, the bus
master will send a twobyte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data
(D7:D0). A 16bit CRC of the command byte, address
bytes, and data byte is computed by the DS2407 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.

DS2407

012099 10/31

If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, a programming pulse (12 volts on the 1Wire bus
for 480

s) is issued by the bus master. Prior to program-

ming, the entire unprogrammed EPROM memory field
will appear as logical 1s. For each bit in the data byte
provided by the bus master that is set to a logical 0, the
corresponding bit in the selected byte of the EPROM
memory is programmed to a logical 0 after the program-
ming pulse has been applied.

After the 480

s programming pulse is applied and the

data line returns to the idle level (5 volts), the bus master
issues eight read time slots to verify that the appropriate
bits have been programmed. The DS2407 responds
with the data from the selected EPROM address sent
least significant bit first. This byte contains the bitwise
logical AND of all data ever written to this address. If the
EPROM byte contains 1s in bit positions where the byte
issued by the master contained 0s, a Reset Pulse
should be issued and the current byte address should
be programmed again. If the DS2407 EPROM byte con-
tains 0s in the same bit positions as the data byte, the
programming was successful and the DS2407 will auto-
matically increment its address counter to select the
next byte in the EPROM memory field. The new two
byte address will also be loaded into the 16bit CRC
generator as a starting value. The bus master will issue
the next byte of data using eight write time slots.

As the DS2407 receives this byte of data into the
scratchpad, it also shifts the data into the CRC genera-
tor that has been preloaded with the current address
and the result is a 16bit CRC of the new data byte and
the new address. After supplying the data byte, the bus
master will read this 16bit CRC from the DS2407 with

sixteen read time slots to confirm that the address
incremented properly and the data byte was received
correctly. If the CRC is incorrect, a Reset Pulse must be
issued and the write sequence must be restarted. If the
CRC is correct, the bus master will issue a programming
pulse and the selected byte in memory will be pro-
grammed.

Note that the initial pass through the write flow chart will
generate an 16bit CRC value that is the result of shift-
ing the command byte into the CRC generator, followed
by the two address bytes, and finally the data byte. Sub-
sequent passes through the write flow chart due to the
DS2407 automatically incrementing its address counter
will generate a 16bit CRC that is the result of loading
(not shifting) the new (incremented) address into the
CRC generator and then shifting in the new data byte.

For both of these cases, the decision to continue (to
apply a program pulse to the DS2407) is made entirely
by the bus master, since the DS2407 will not be able to
determine if the 16bit CRC calculated by the bus mas-
ter agrees with the 16bit CRC calculated by the
DS2407. If an incorrect CRC is ignored and a program
pulse is applied by the bus master, incorrect program-
ming could occur within the DS2407. Also note that the
DS2407 will always increment its internal address
counter after the receipt of the eight read time slots used
to confirm the programming of the selected EPROM
byte. The decision to continue is again made entirely by
the bus master. Therefore if the EPROM data byte does
not match the supplied data byte but the master contin-
ues with the write command, incorrect programming
could occur within the DS2407. The write command
sequence can be ended at any point by issuing a Reset
Pulse.

F0h

READ

MEMORY

BUS MASTER T

TA1 (T7:T0)

BUS MASTER T

TA2 (T15:T8)

DS2407 SETS MEMORY

ADDRESS = (T15:T0)

BUS MASTER R

DATA FROM

DATA MEMORY

BUS MASTER

RESET

END

OF DATA

MEMORY

DS2407 INCREMENTS

ADDRESS COUNTER

BUS MASTER R

CRC16 OF COMMAND,

ADDRESS, DATA

BUS MASTER

RESET

BUS MASTER

1'S

BUS MASTER

RESET

MASTER T

MEMORY

FUNCTION COMMAND

DS2407 T

PRESENCE PULSE

BUS MASTER

RESET

A5h

EXTENDED

READ MEMORY

BUS MASTER T

TA1 (T7:T0)

BUS MASTER T

TA2 (T15:T8)

DS2407 SETS MEMORY

ADDRESS = (T15:T0)

BUS MASTER R

REDIR. BYTE

CRC

CORRECT

DS2407 INCREMENTS

ADDRESS COUNTER

BUS MASTER R

DATA FROM

DATA MEMORY

BUS MASTER

RESET

END OF

PAGE

BUS MASTER R

CRC16

OF PRECEDING PAGE OF DATA

END OF

DATA

MEMORY

BUS MASTER

RESET

BUS MASTER

1'S

DS2407 INCREMENTS

ADDRESS COUNTER

BUS MASTER R

CRC16 OF COMMAND,

ADDRESS, REDIR. BYTE

(1ST PASS)

CRC16 OF REDIR. BYTE (SUBSEQUENT

PASSES)

BUS MASTER

RESET

CRC

CORRECT

LEGEND:

DECISION MADE
BY THE MASTER

DECISION MADE

BY DS2407

TO FIGURE 6
SECOND PART

DS2407

012099 11/31

MEMORY FUNCTION FLOW CHART Figure 6

0Fh

WRITE

MEMORY

BUS MASTER T

TA1 (T7:T0)

BUS MASTER T

TA2 (T15:T8)

BUS MASTER R

CRC16

OF COMMAND, ADDRESS,

DATA (1

PASS)

CRC16 OF ADDRESS, DATA

(SUBSEQUENT PASSES)

CRC

CORRECT

BUS MASTER T

DATA BYTE (D7:D0)

BUS MASTER T

PROGRAM PULSE

BUS MASTER R

BYTE FROM EPROM

END OF

DATA MEMORY

DS2407 INCREMENTS

ADDRESS COUNTER

DS2407 LOADS NEW
ADDRESS INTO CRC

GENERATOR

55h

WRITE

STATUS

BUS MASTER T

TA1 (T7:T0)

BUS MASTER T

TA2 (T15:T8)

CRC

CORRECT

BUS MASTER T

DATA BYTE (D7:D0)

BUS MASTER T

PROGRAM PULSE

BUS MASTER R

BYTE FROM EPROM

BUS MASTER

RESET

EPROM BYTE

CORRECT

ADDRESS

DS2407 INCREMENTS

ADDRESS COUNTER

DS2407 LOADS NEW
ADDRESS INTO CRC

GENERATOR

EPROM BYTE

CORRECT

BUS MASTER R

CRC16

OF COMMAND, ADDRESS,

DATA (1

PASS)

CRC16 OF ADDRESS, DATA

(SUBSEQUENT PASSES)

DS2407 COPIES

SCRATCHPAD

TO STATUS EPROM

DS2407 COPIES

SCRATCHPAD

TO DATA EPROM

BUS MASTER T

8 READ TIME SLOTS

OR PROGRAM PULSE

DS2407 COPIES

SCRATCHPAD TO

VOLATILE STATUS

BUS MASTER R

BYTE

FROM VOLATILE

STATUS

DS2407 T

PRESENCE PULSE

LEGEND:

DECISION MADE
BY THE MASTER

DECISION MADE

BY DS2407

TO FIGURE 6
SECOND PART

FROM FIGURE 6
FIRST PART

DS2407

012099 12/31

MEMORY FUNCTION FLOW CHART Figure 6 (cont'd)

AAh

READ STATUS

BUS MASTER T

TA1 (T7:T0)

BUS MASTER T

TA2 (T15:T8)

DS2506 SETS STATUS ADDRESS

= (T15:T0)

BUS MASTER R

DATA

FROM

STATUS MEMORY

BUS MASTER

RESET

END OF

STATUS MEMORY

DS2506 INCREMENTS

ADDRESS COUNTER

BUS MASTER

RESET

BUS MASTER

1'S

BUS MASTER

RESET

BUS MASTER R

CRC16

OF COMMAND,

ADDRESS, DATA

F5h

CHANNEL

ACCESS

BUS MASTER T

CONTROL BYTE 1

BUS MASTER T

CONTROL BYTE 2

BUS MASTER R

CHANNEL INFO BYTE

BUS MASTER

RESET

MODE

BUS MASTER T

DATA

TO CHANNEL F/F

BUS MASTER R

DATA FROM PIOs

BUS MASTER

RESET

CRC
DUE

BUS MASTER

RESET

DS2407 INCR. CRC

BYTE COUNTER

BUS MASTER R

CRC16 OF

COMMAND, CONTROL, DATA

(1ST PASS)

CRC16 OF DATA

(SUBSEQUENT PASSES)

BUS MASTER

RESET

DS2407 CLEARS

CRC BYTE COUNTER

R/W TOGGLING

ENABLED

DS2407 TOGGLES

READ/WRITE MODE

BUS MASTER

RESET

DS2407 T

PRESENCE PULSE

DS2407 T

PRESENCE PULSE

WRITE

READ

SEE CHANNEL CONTROL BYTE 1

AND FIGURE 7A.

FROM FIGURE 6
SECOND PART

CRC

ENABLED

DS2407

012099 13/31

MEMORY FUNCTION FLOW CHART Figure 6 (cont'd)

DS2407

012099 14/31

WRITE MEMORY [0Fh]

The Write Memory command is used to program the
1024bit EPROM data field. The details of the functional
flow chart are described in the section "WRITING
EPROM MEMORY". The data memory address range
is 0000h to 007Fh. If the bus master sends a starting
address higher than this, the nine most significant
address bits are set to zeros by the internal circuitry of
the chip. This will result in a mismatch between the CRC
calculated by the DS2407 and the CRC calculated by
the bus master, indicating an error condition.

WRITE STATUS [55h]

The Write Status command is used to program the Sta-
tus Memory field, which includes specification of pow-
eron default settings of the Conditional Search and the
channel flipflops as well as dynamic changes of the
Conditional Search Settings and channel flipflops. The
details of the functional flow chart are described in the
section "WRITING EPROM MEMORY".

The Status Memory address range is 0000h to 0007h.
The general programming algorithm is valid for the
EPROM section of the Status Memory (addresses 0 to
6) only. Status Memory Address 7 consists of SRAM
cells rather than EPROM. As a consequence, writing to
this location does not require a 12V programming pulse
and the bits 0 to 6 can be reprogrammed to any value
without limitation. Bit 7 is readonly; attempts to write to
it are ignored. The function flow for writing to status
memory location 7 is basically the same as for the
EPROM Status Memory Bytes. However, the program-
ming pulse may be, but need not be, replaced by send-
ing 8 Read Data Time Slots.

READ STATUS [AAh]

The Read Status command is used to read data from
the Status Memory field. The functional flow chart of this
command is identical to the Read Memory command.
Since the Status Memory is only 8 bytes, the DS2407
will send the 16bit CRC after the last byte of status
information has been transmitted.

CHANNEL ACCESS [F5h]

The Channel Access command is used to access the
PIO channels to sense the logical status of the output
node and the output transistor and to change the status
of the output transistor. The bus master will follow the
command byte with two Channel Control Bytes and will
receive back the Channel Info byte.

The Channel Control bytes allow the master to select a
PIOchannel to communicate with, to specify commu-
nication parameters and to reset the activity latches.
Figure 7 shows the details. The bits CHS0 and CHS1
(Channel Control Byte 1) select the channels to commu-
nicate with. One can select one of the two channels or
both channels together.

The codes for CHS0 and CHS1 are as follows:

CHS1

CHS0

0 (not

allowed)

channel A only

channel B only

both channels interleaved

When reading a single channel only, the logic level at the
selected PIO is sampled at the beginning of each read
time slot (Figure 9a) and immediately signaled through
the 1Wire line. Because the PIO logic levels are
sensed at the beginning of the time slot, transitions at
the PIO during the time slot are not seen by the bus mas-
ter. When writing to a single channel, the selected PIO
will show the new status after (but not necessarily
immediately after) the 1Wire line has returned to its idle
level of typically 5V (see Figure 9a). If the bus master
transmits a 1 (Write One Time Slot), the output transistor
of the selected channel will change its status after time
td1, which is 15

s to 60

s after the begin of the time

slot. If the bus master transmits a 0 (Write Zero Time
Slot), the output transistor will change its status with a
delay of td0 after the 1Wire line has returned to its idle
level. The value of td0 may vary between 200 and 300
ns (see Figure 9a). Depending on the load conditions,
there may be additional delay until the voltage at the PIO
reaches a new logical level.

If one is communicating with both channels, the Inter-
leave Control Bit IC controls when data is sampled and
when data arrives at the PIO pins. There is an asynchro-
nous mode (IC = 0) and a synchronous mode (IC = 1).
For the asynchronous mode, both channels are
accessed in an alternating way. For the synchronous
mode, both channels are accessed simultaneously.

When reading in the asynchronous mode each channel
is sampled alternately at the start of each Read Time
Slot, beginning with channel A. The logic level detected
at the PIO is immediately transmitted to the master dur-
ing the same time slot. When reading in the synchro-
nous mode, both channels will be sampled at the same
time; the data bit from channel A will be sent to the mas-

DS2407

012099 15/31

ter immediately during the same time slot while the data
bit from channel B follows with the next time slot which
does not sample the PIOs. Both channels will be
sampled again with the time slot that follows the trans-
mission of the data bit from PIOB (Figure 9b).

When writing in the asynchronous mode, each channel
will change its status independently of the other. The
change of status occurs with the same timing relations
as for communication with one channel. However, every
second write time slot addresses the same channel.
The first time slot is directed to channel A, the second to
channel B, the next to channel A and so on. As a conse-
quence, in asynchronous mode both PIOs can never
change their status at the same time. When writing in
the synchronous mode, both channels operate
together. After the new values for both channels have
arrived at the DS2407 the change of status at both chan-
nels occurs with the same timing relations as for com-
munication with one channel. As with the asynchronous
mode, every second write time slot contains data for the
same channel. The first time slot addresses channel A,
the second channel B and so on. Depending on the data
values, in the synchronous mode both PIOs can change
their status at the same time (Figure 9c). In any of these
cases, the information of channel A and channel B will
appear alternating on the 1Wire line, always starting
with channel A. By varying the idletime between time
slots on the 1Wire line one has full control over the time
points of sampling and the waveforms generated at the
PIOpins when writing to the device.

The TOG bit of Channel Control Byte 1 specifies if one is
always reading or writing (TOG = 0) or if one is going to
change from reading to writing or vice versa after every
data byte that has been sent to or received from the
DS2407 (TOG = 1). When accessing one channel, one
byte is equivalent to eight reads from or writes to the
selected PIO pin. When accessing two channels, one
byte is equivalent to four reads or writes from/to each
channel.

The initial mode (reading or writing) for accessing the
PIO channels is specified in the IM bit. For reading, IM
has to be set to 1, for writing IM needs to be 0. If the TOG
bit is set to 0, the device will always read or write as spe-
cified by the IM bit. If TOG is 1, the device will use the
setting of IM for the first byte to be transmitted and will
alternate between reading and writing after every byte.
Figure 7c illustrates the effect of TOG and IM for one
channel as well as for twochannel operation.

Bit 7 of the Channel Control Byte 1 allows resetting of
the activity latch of each channel. The activity latch is set
with the first negative or positive edge detected on its
associated PIO channel. Both activity latches are
cleared simultaneously if bit 7 of the Channel Control
Byte 1 is 1. The activity latches are not changed if this bit
is 0.

Channel Control Byte 1 also controls the internal CRC
generator to safeguard data transmission between the
bus master and the DS2407 for channel access. It does
not affect reading from or writing to the memory sections
of the DS2407. The CRC control bits (bit 0 and bit 1) can
be set to create and protect data packets that have the
size of 8 bytes or 32 bytes. If desired, the device can
safeguard even single bytes by a 16bit CRC. This set-
ting, however, is recommended only if the data is limited
to one byte since it would reduce the sampling rate to
one third of the maximum possible value.

The CRC control codes are as follows:

CRC1

CRC0

CRC disabled (no CRC at all)

CRC after every byte

CRC after 8 bytes
(status page size)

CRC after 32 bytes
(data page size)

The CRC provides a high level of data safeguarding and
is more efficient for verification than "read after write". A
detailed description of CRCs is found in the "Book of
DS19xx iButton Standards". If the CRC is disabled, the
CRCrelated sections in the flow chart are skipped.

Channel Control Byte 2 is reserved for future develop-
ment. The bus master should always send an FFh for
the second Channel Control Byte.

The Channel Info byte (Figure 8) which the bus master
receives after the Channel Control bytes have been
transmitted indicates the status of the channel flip
flops, the PIO pins, the activity latches as well as the
availability of channel B and external power supply.
Reading 0 for both the channel flipflop and the sensed
level indicates that the output transistor of the PIO is
pulling the node low. To be able to read from a PIO chan-
nel, the output transistor needs to be nonconducting,
which is equivalent to a 1 for the channel flipflop. Sam-
pling the level of PIO A and B is done at the same time
(synchronous) for the Channel Info Byte. If channel B is

DS2407

012099 16/31

available, bit 6 of the Channel Info Byte reads 1. For
1channel versions of the DS2407, the PIO B sensed
level, channel flipflop value, and activity latch value
should be ignored. Without an external supply, the sup-

ply indication bit (bit 7) reads 0. As long as the voltage
applied to the V

pin is high enough to operate the

device this bit will read 1.

CHANNEL CONTROL BYTE 1 Figure 7a

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Activity

latch reset

TOG

CHS1

CHS0

CRC1

CRC0

CHANNEL CONTROL BYTE 2 Figure 7b

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

THE EFFECT OF TOGGLE MODE AND INITIAL MODE Figure 7c

TOG

CHANNELS

EFFECT

one channel

Write all bits to the selected channel.

one channel

Read all bits from the selected channel.

one channel

Write eight bits, read eight bits, write, read, etc. to/
from the selected channel.

one channel

Read eight bits, write eight bits, read, write, etc.
from/to the selected channel.

two channels

Repeat: four times (write A, write b)

two channels

Repeat: four times (read A, read B)

two channels

Four times: (write A, write B), four times: (read A,
read B), write, read, etc.

two channels

Four times: (read A, read B), four times: (write A,
write B), read, write, etc.

CHANNEL INFO BYTE Figure 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Supply

Indication

0=no sup-

ply

Number of

Channels

0=channel A

only

PIOB

Activity

Latch

PIOA

Activity

Latch

PIOB

Sensed

Level

PIOA

Sensed

Level

PIOB

Channel

FlipFlop Q

PIOA

Channel

FlipFlop Q

DS2407

012099 18/31

TWOCHANNEL WRITE Figure 9C

1WIRE

PIOA

PIOB

PIOA

PIOB

SYNCHRONOUS MODE

ASYNCHRONOUS MODE

td1

s < td1 < 60

200 ns < td0 < 300 ns

1WIRE BUS SYSTEM

The 1Wire bus is a system which has a single bus mas-
ter and one or more slaves. In all instances, the DS2407
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1Wire signaling (signal type and
timing). A 1Wire protocol defines bus transactions in
terms of the bus state during specified time slots that are
initiated on the falling edge of sync pulses from the bus
master. For a more detailed protocol description, please
refer to Chapter 4 of the Book of DS19xx iButton Stan-
dards.

HARDWARE CONFIGURATION

The 1Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1Wire bus must have an open drain
connection or 3state outputs. The DS2407 is an open
drain part with an internal circuit equivalent to that
shown in Figure 10. The bus master can be the same
equivalent circuit. If a bidirectional pin is not available,
separate output and input pins can be tied together.

The bus master requires a pullup resistor at the master
end of the bus, with the bus master circuit equivalent to
the one shown in Figures 11a and 11b. The value of the
pullup resistor should be approximately 5k

for short

line lengths. The interface between bus master and
1Wire bus may be reduced to a single pullup resistor

(open drain master) or two resistors plus transistor
(TTLtype master) if the EPROM section of the DS2407
is already programmed before the final installation.

A multidrop bus consists of a 1Wire bus with multiple
slaves attached. The 1Wire bus has a maximum data
rate of 16.3k bits per second. If the bus master is also
required to perform programming of the EPROM por-
tions of the DS2407, a programming supply capable of
delivering up to 10 milliamps at 12 volts for 480

s is

required. NonEPROM devices cannot be present dur-
ing programming. The idle state for the 1Wire bus is
high. If, for any reason, a transaction needs to be sus-
pended, the bus MUST be left in the idle state if the
transaction is to resume. If this does not occur and the
bus is left low for more than 120

s, one or more of the

devices on the bus may be reset. If the 1Wire bus
remains low for more than 5 ms and the DS2407 is not
powered externally it may lose its current status and
switch off both PIOs.

TRANSACTION SEQUENCE

The sequence for accessing the DS2407 via the 1Wire
port is as follows:

Initialization

ROM Function Command

Memory Function Command

Read Memory/Write Memory or Channel Access

DS2407

012099 19/31

INITIALIZATION

All transactions on the 1Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by a presence pulse(s) transmitted by the slave(s).

The presence pulse lets the bus master know that the
DS2407 is on the bus and is ready to operate. For more
details, see the "1Wire Signaling" section.

ROM FUNCTION COMMANDS

Once the bus master has detected a presence, it can
issue one of the five ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 12):

Read ROM [33h]

This command allows the bus master to read the
DS2407's 8bit family code, unique 48bit serial num-
ber, and 8bit CRC. This command can be used only if
there is a single DS2407 on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wiredAND result).

Match ROM [55h]

The match ROM command, followed by a 64bit ROM
sequence, allows the bus master to address a specific
DS2407 on a multidrop bus. Only the DS2407 that
exactly matches the 64bit ROM sequence will respond
to the subsequent memory function command. All
slaves that do not match the 64bit ROM sequence will
wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.

Skip ROM [CCh]

This command can save time in a single drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64bit ROM code. If
more than one slave is present on the bus and a read
command is issued following the Skip ROM command,
data collision will occur on the bus as multiple slaves
transmit simultaneously (open drain pulldowns will
produce a wiredAND result).

Search ROM [F0h]

When a system is initially interrogated, the bus master
may not know the number of devices on the 1Wire bus
or their 64bit ROM codes. The Search ROM command
allows the bus master to use a process of elimination to
identify the 64bit ROM codes of all slave devices on the
bus. This process of elimination involves repeated
application of a simple threestep procedure where the
bus master starts by reading a bit position in the 64bit
ROM, followed by reading the complement of that bit
position, and finally writing to all the devices still
involved in the search the desired logic value for that bit
position. A detailed example and a flowchart for the
search algorithm can be found in the "Book of DS19xx
iButton Standards."

After one complete pass, the bus master knows the con-
tents of the 64bit ROM in one device. Subsequent
passes will reveal the total number of devices and their
individual ROM codes. In addition, after each complete
pass of the search that successfully determines the
64bit ROM for a specific device on the multidrop bus,
that particular device can be individually accessed as if
a Match ROM had been issued since all other devices
will have dropped out of the search process and are
waiting for a reset pulse.

DS2407

012099 20/31

DS2407 EQUIVALENT CIRCUIT Figure 10

Typ.

100

MOSFET

DATA

GROUND

RESET

GROUND

10M

Typ.

"1"

PIO

ACTIVITY

LATCH

TO PIO

CONTROL

1WIRE DATA

FROM PIO
CONTROL

EDGE

DETECTOR

CHANNEL

FLIPFLOP

PIO CHANNEL

1WIRE INTERFACE

BUS MASTER CIRCUIT Figure 11

The interface is reduced to the 5k

pullup resistor if one does not intend to program the EPROM cells.

BUS MASTER

TTLEquivalent

Port Pins

B) Standard TTL

PUP

PROGRAMMING PULSE

12V

(10 mA min.)

BUS MASTER

PUP

DS5000 OR 8051 EQUIVALENT

Open Drain

Port Pin

A) Open Drain

12V

TO DATA CONNECTION
OF DS2506

10k

PGM

2N7000

470 pF

VP0300L

VP0106N3

BSS110

CAPACITOR ADDED TO REDUCE
COUPLING ON DATA LINE DUE TO
PROGRAMMING SIGNAL SWITCHING

TO DATA CONNECTION
OF DS2507

The diode and Programming Pulse circuit are not required if one does not intend to program the EPROM cells.

DS2407

012099 21/31

ROM FUNCTIONS FLOW CHART Figure 12

33h

READ ROM

COMMAND

55h

MATCH ROM

COMMAND

F0h

SEARCH ROM

COMMAND

CCh

SKIP ROM

COMMAND

DS2407 T

FAMILY CODE

1 BYTE

BIT 0

MATCH?

BIT 0

MATCH?

BIT 1

MATCH?

BIT 1

MATCH?

BIT 63

MATCH?

BIT 63

MATCH?

DS2407 T

SERIAL NUMBER

6 BYTES

DS2407 T

CRC BYTE

DS2407 T

BIT 0

DS2407 T

BIT 0

DS2407 T

BIT 1

DS2407 T

BIT 1

DS2407 T

BIT 63

DS2407 T

BIT 63

MASTER T

BIT 1

MASTER T

BIT 0

MASTER T

BIT 0

MASTER T

BIT 1

MASTER T

BIT 63

MASTER T

BIT 63

MASTER T

RESET PULSE

DS2407 T

PRESENCE PULSE

MASTER T

ROM

FUNCTION COMMAND

MASTER T

MEMORY

FUNCTION COMMAND

(SEE FIGURE 6)

ECh

CONDITIONAL

BIT 0

MATCH?

BIT 1

MATCH?

BIT 63

MATCH?

DS2407 T

BIT 0

DS2407 T

BIT 0

DS2407 T

BIT 1

DS2407 T

BIT 1

DS2407 T

BIT 63

DS2407 T

BIT 63

MASTER T

BIT 0

MASTER T

BIT 1

MASTER T

BIT 63

CONDITION

FULFILLED

DS2407

012099 22/31

Conditional Search ROM [ECh]

The Conditional Search ROM command operates simi-
larly to the Search ROM command except that only
devices fulfilling the specified condition will participate in
the search. The condition is specified by the bit func-
tions CSS0 to CSS4 in Status Memory location 7. The
poweron default settings of these bits are stored in
EPROM in Status Memory location 6. If this EPROM
byte is not programmed, all CSS bits will be 1s. The
Conditional Search ROM provides an efficient means
for the bus master to determine devices in a multidrop
system that have to signal a status change, e.g. the
opening of a window in a building control application.
After each pass of the Conditional Search that success-
fully determined the 64bit ROM for a specific device on
the multidrop bus, that particular device can be individu-
ally accessed as if a Match ROM had been issued since
all other devices will have dropped out of the search pro-
cess and are waiting for a reset pulse.

For the conditional search, one can specify the polarity
(HIGH or LOW; CSS0), the source (PIOpin, channel
flip flop or activity latch; CSS1, CSS2) and the channel
of interest (A, B or the logical OR of A, B; CSS3, CSS4).
Figure 13 shows a table of all qualifying conditions and
the required settings for CSS0 to CSS4.

The activity latch (Figure 10) captures an event for
interrogation by the bus master at a later time. In this
way, the bus master needs not to poll devices continu-
ously. The activity latch is cleared to 0 when the device
powers up and is set to 1 with the first negative or posi-
tive edge detected on the associated PIO channel. The
activity latch can also be cleared by writing a 1 into bit 7
of the Channel Control Byte 1. When using the activity
latch the output transistor of the selected channel
should be nonconducting. Otherwise signals applied
to the PIO pin will be shorted to ground by the low imped-
ance of the output transistor.

The channel of interest is specified by the Channel
Select bits CSS3 and CSS4. The sampling of the source
within the selected channel will take place on comple-
tion of the Conditional Search command byte. The
Channel selection codes are as follows:

CSS4, CSS3

Channel

Selection

neither channel selected

channel A only

channel B only

channel A OR channel B

If both CSS3 and CSS4 are 1, the logical values of the
selected signal source of both channels are ORed and
the result is compared to specified polarity. If, for exam-
ple, the specified polarity is 0, the signal source of both
channels must be 0 to allow the device to respond to the
Conditional Search. If both CSS3 and CSS4 are 0 nei-
ther channel is selected. Under this condition the device
will always respond to the Conditional Search if the
polarity bit CSS0 is 0, disregarding the status of the
selected source. If neither channel is selected and
CSS0 = 1, the device will ignore the Conditional Search
but will respond to the regular Search ROM command.

The source selection for the Conditional Search is done
through the Source Select bits CSS1 and CSS2. The
codes for these bits are as follows:

CSS2, CSS1

Source

Selection

Hidden Mode

Activity Latch

channel flip flop

PIO Status

Setting both CSS1 and CSS2 to 0 will put the device into
a "Hidden Mode" where it keeps its status but only
responds to the Match ROM (always) and Conditional
Search command (only if the polarity bit CSS0 is set to
1). While in "Hidden Mode" the device will never give a
Presence Pulse. When powering up into the "Hidden
Mode", i.e., when bits 1 and 2 of status byte 6 have been
programmed to 0, the device will give one Presence
Pulse for every powerup sequence. If the device is in
Hidden Mode and the polarity bit is set to 0, the device
will not participate in the Conditional Search. As long as
the device is not programmed to powerup into "Hidden
Mode" the "Hidden Mode" can always be ended by a
poweron reset. Otherwise the only way to get the
device out of "Hidden Mode" is by remembering and
matching its 64bit registration number and setting
CSS1 or CSS2 to 1.

The Conditional Search Polarity is specified by CSS0. If
CSS0 is 0, the DS2407 will respond to a Conditional
Search command if the status of the selected source for
the specified channel is a logic 0. If CSS0 is set to 1, the
source level needs to be a logic 1.

For 1channel versions of the DS2407 the channel B
input will always be a logic 0 level. CSS4 should not be
set to 1 therefore to avoid unwanted influence from

DS2407

012099 23/31

channel B. The bus master can determine the availabil-
ity of channel B from bit 6 of the Channel Info byte.

The poweron default settings for the conditional
search become valid after the device has received any

ROM function command byte, even an invalid one, and
can be modified by writing to the appropriate Status
Memory location. As long as the device remains pow-
ered up, the modified search conditions are available for
use at any time.

QUALIFYING CONDITIONS FOR CONDITIONAL SEARCH Figure 13

DESCRIPTION

CONDITIONAL SEARCH SELECT CODE

CONDITION

CHANNEL

CHANNEL SELECT

SOURCE SELECT

POLARITY

CONDITION

CHANNEL

CSS4

CSS3

CSS2

CSS1

CSS0

Hidden Mode

neither one

don't care

Unconditional

neither one

at least one of these bits

needs to be 1

Activity Latch = 0

Activity Latch = 1

Channel FF = 0
(transistor on)

Channel FF = 1
(transistor off)

PIO Low

PIO High

Activity Latch = 0

Activity Latch = 1

Channel FF = 0
(transistor on)

Channel FF = 1
(transistor off)

PIO Low

PIO High

Activity Latch = 0

A or B

Activity Latch = 1

A or B

Channel FF = 0
(transistor on)

A or B

Channel FF = 1
(transistor off)

A or B

PIO Low

A or B

PIO High

A or B

DS2407

012099 24/31

INITIALIZATION PROCEDURE "RESET AND PRESENCE PULSES" Figure 14

RSTH

RSTL

PULLUP

PULLUP MIN

IH MIN

IL MAX

PDH

PDL

RESISTOR

MASTER

DS2407

MASTER R

"PRESENCE PULSE"

MASTER T

"RESET PULSE"

480

s < t

RSTL

480

s < t

RSTH

(includes recovery time)

s < t

PDH

< 60

s < t

PDL

< 240

* In order not to mask interrupt signalling by other devices on the 1Wire bus, t

RSTL

+ t

should always be less than

960

s. t

RSTL

should be limited to maximum 5 ms. Otherwise the DS2407 may perform a poweron reset cycle.

READ/WRITE TIMING DIAGRAM Figure 15

Writeone Time Slot

REC

LOW1

PULLUP

PULLUP MIN

IH MIN

IL MAX

DS2407

SAMPLING WINDOW

SLOT

RESISTOR

MASTER

DS2407

s < t

SLOT

< 120

s < t

LOW1

< 15

s < t

REC

DS2407

012099 25/31

READ/WRITE TIMING DIAGRAM Figure 15 (cont'd)

Writezero Time Slot

PULLUP

PULLUP MIN

IH MIN

IL MAX

SLOT

REC

LOW0

DS2407

SAMPLING WINDOW

s < t

LOW0

< t

SLOT

< 120

s < t

REC

Readdata Time Slot

PULLUP

PULLUP MIN

IH MIN

IL MAX

SLOT

REC

RDV

LOWR

s < t

SLOT

< 120

s < t

LOWR

< 15

0 < t

RELEASE

< 45

s < t

REC

RDV

= 15

< 1

RELEASE

MASTER SAMPLING

WINDOW

RESISTOR

MASTER

DS2407

1WIRE SIGNALING

The DS2407 requires strict protocols to insure data
integrity. The protocol consists of five types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1, Read Data and Pro-
gram Pulse. All these signals except presence pulse are
initiated by the bus master. The initialization sequence
required to begin any communication with the DS2407
is shown in Figure 14. A reset pulse followed by a pres-
ence pulse indicates the DS2407 is ready to accept a
ROM command. The bus master transmits (TX) a reset

pulse (t

RSTL

, minimum 480

s). The bus master then

releases the line and goes into receive mode (RX). The
1Wire bus is pulled to a high state via the pullup resis-
tor. After detecting the rising edge on the data pin, the
DS2407 waits (t

PDH

, 1560

s) and then transmits the

presence pulse (t

PDL

, 60240

s). If the device is pro-

grammed to powerup into the "Hidden Mode", the
presence pulse will be observed only once during the
powerup phase. With every subsequent reset pulse no
presence pulse will be transmitted.

DS2407

012099 26/31

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated
in Figure 15. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS2407 to the master by triggering a
delay circuit in the DS2407. During write time slots, the
delay circuit determines when the DS2407 will sample
the data line. For a read data time slot, if a "0" is to be
transmitted, the delay circuit determines how long the
DS2407 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is an "1", the device
will leave the read data time slot unchanged.

PROGRAM PULSE

To copy data from the 8bit scratchpad to the EPROM
Data or Status Memory, a program pulse of 12 volts is
applied to the data line after the bus master has con-
firmed that the CRC for the current byte is correct. Dur-
ing programming, the bus master controls the transition
from a state where the data line is idling high via the
pullup resistor to a state where the data line is actively
driven to a programming voltage of 12 volts providing a
minimum of 10 mA of current to the DS2407. This pro-
gramming voltage (Figure 16) should be applied for 480

s, after which the bus master should return the data

line to an idle high state controlled by the pullup resis-
tor. Note that due to the high voltage programming
requirements for any 1Wire EPROM device, it is not
possible to multidrop nonEPROM based 1Wire
devices (e.g. DS1990A, DS1992) with the DS2407 dur-
ing programming. An internal diode within the non
EPROM based 1Wire devices will attempt to clamp the
data line at approximately 8 volts and could potentially
damage these DS199x devices.

CRC GENERATION

With the DS2407 there are two different types of CRCs
(Cyclic Redundancy Checks). One CRC is an 8bit type
and is stored in the most significant byte of the 64bit
ROM. The bus master can compute a CRC value from

the first 56 bits of the 64bit ROM and compare it to the
value stored within the DS2407 to determine if the ROM
data has been received errorfree by the bus master.
The equivalent polynomial function of this CRC is:
X

+ X

+ 1. This 8bit CRC is received in the true

(noninverted) form when reading the ROM of the
DS2407. It is computed at the factory and lasered into
the ROM.

The other CRC is a 16bit type, generated according to
the standardized CRC16polynomial function X

+ X

+ 1. This CRC is used for error detection when

reading Data Memory, Status Memory or when commu-
nicating with PIO channels. It is the same type of CRC
as is used with NVRAM based iButtons for error detec-
tion within the iButton Extended File Structure. In con-
trast to the 8bit CRC, the 16bit CRC is always
returned in the complemented (inverted) form. A CRC
generator inside the DS2407 chip (Figure 17) will calcu-
late a new 16bit CRC at every situation shown in the
command flow chart of Figure 6.

The DS2407 provides this CRCvalue to the bus mas-
ter to validate the transfer of command, address, and
data to and from the bus master. When reading the data
memory of the DS2407 with the Read Memory com-
mand, the 16bit CRC is only transmitted at the end of
the memory. This CRC is generated by clearing the
CRC generator, shifting in the command, low address,
high address and every data byte starting at the first
addressed memory location and continuing until the end
of the implemented data memory is reached.

When reading the Status Memory with the Read Status
command, the 16bit CRC is transmitted at the end of
the 8 byte page of the Status Memory. The 16bit CRC
will be generated by clearing the CRC generator, shift-
ing in the command byte, low address, high address and
the data bytes beginning at the first addressed memory
location and continuing until the last byte of the EPROM
Status Memory is reached.

DS2407

012099 27/31

When reading the data memory of the DS2407 with the
Extended Read Memory command, there are two situa-
tions where a 16bit CRC is transmitted. One 16bit
CRC follows each Redirection Byte, another 16bit
CRC is received after the last byte of a memory data
page is read. The CRC at the end of the memory page is
always the result of clearing the CRC generator and
shifting in the data bytes beginning at the first addressed
memory location of the EPROM data page until the last
byte of this page. With the initial pass through the
Extended Read Memory flow chart the 16bit CRC
value is the result of shifting the command byte into the
cleared CRC generator, followed by the two address
bytes and the Redirection Byte. Subsequent passes
through the Extended Read Memory flow chart will gen-
erate a 16bit CRC that is the result of clearing the CRC
generator and then shifting in only the Redirection Byte.

When writing to the DS2407 (either data memory or Sta-
tus Memory), the bus master receives a 16bit CRC to
verify that the data transfer was correct before applying
the programming pulse. With the initial pass through the
Write Memory/Status flow chart the 16bit CRC will be
generated by clearing the CRCgenerator, shifting in
the command, low address, high address and the data
byte. Subsequent passes through the Write Memory/
Status flow chart due to the DS2407 automatically incre-
menting its address counter will generate a 16bit CRC
that is the result of loading (not shifting) the new
(incremented) address into the CRC generator and then
shifting in the new data byte.

When communicating with a PIO channel using the
Channel Access command, one can select if and how
often a 16bit CRC will be added to the data stream.
This CRC selection is specified in the Channel Control
byte 1 and may be different every time the Channel
Access command is issued by the bus master. Depend-
ing on the CRC selection, the device can generate a
CRC after every byte that follows the Channel Info byte,
after each block of eight bytes or after each block of 32
bytes. If the CRC is enabled, with the initial pass through
the Channel Access flow chart the 16bit CRC will be
generated by clearing the CRCgenerator, shifting in
the command, Channel Control Bytes 1 and 2, Channel
Info Byte and the specified amount of data bytes (1, 8 or
32). Subsequent passes through the Channel Access
flow chart will generate a 16bit CRC that is the result of
clearing the CRC generator and then shifting in the new
data bytes. This algorithm is valid for all accesses to the
PIO channels, continuous reading or writing as well as
toggling between read and write.

The comparison of CRC values and decision to con-
tinue with an operation are determined entirely by the
bus master. There is no circuitry on the DS2407 that pre-
vents a command sequence from proceeding if the CRC
stored in or calculated by the DS2407 does not match
the value generated by the bus master. For more details
on generating CRC values including example imple-
mentations in both hardware and software, see the
"Book of DS19xx iButton Standards".

PROGRAM PULSE TIMING DIAGRAM Figure 16

LINE TYPE LEGEND:

PULLUP

GND

480

NORMAL 1Wire
COMMUNICATION ENDS

NORMAL 1Wire
COMMUNICATION RESUMES

Bus master active high
(12V @ 10 mA)

Resistor pullup

DS2407

012099 29/31

ABSOLUTE MAXIMUM RATINGS*

Voltage on DATA or PIOA to Ground

0.5V to +13.0V

Voltage on V

or PIOB to Ground

0.5V to +6.5V

Operating Temperature

C to +85

Storage Temperature

C to +125

Soldering Temperature

260

C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS DATA PIN

( V

PUP

=2.8V to 6.0V; 40

C to +85

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1

2.2

1, 6

Logic 0

0.3

+0.8

1, 13

Output Logic Low @ 4 mA

0.4

Output Logic High

PUP

6.0

1, 2

Input Load Current

3, 14

Programming Voltage @ 10 mA

11.5

12.0

DC ELECTRICAL CHARACTERISTICS PIO PINS

( V

PUP

=2.8V to 6.0V; 40

C to +85

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1 (A)

IHA

2.2

1, 6, 16

Logic 0 (A)

ILA

0.3

+0.6

Output Sink Current @ 0.4V (A)

See graph on page 31

11, 12, 15

Output Logic High (A)

OHA

PUPA

12.0

1, 2

Logic 1 (B)

IHB

2.2

1, 6, 16

Logic 0 (B)

ILB

0.3

+0.4

Output Sink Current @ 0.4V (B)

See graph on page 31

Output Logic High (B)

OHB

PUPB

6.0

1, 2

Input Resistance

DC ELECTRICAL CHARACTERISTICS V

PUP

=2.8V to 6.0V; 40

C to +85

C )

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Logic 1

IHC

2.8

1, 10

Logic 0

ILC

0.3

+0.8

Input Current

4.0

PIOA,

PIOB

1WIRE

SUA

SUB

DS2407

012099 30/31

CAPACITANCE

=25

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Capacitance DATA Pin

800

Capacitance PIOA Pin

100

Capacitance PIOB Pin

Capacitance V

AC ELECTRICAL CHARACTERISTICS

( V

PUP

=2.8V to 6.0V; 40

C to +85

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Time Slot

SLOT

120

Write 1 Low Time

LOW1

Write 0 Low Time

LOW0

120

Read Data Valid

RDV

exactly 15

Release Time

RELEASE

Read Data Setup DATA

Recovery Time

REC

Reset Time High

RSTH

480

Reset Time Low

RSTL

480

5000

Presence Detect High

PDHIGH

Presence Detect Low

PDLOW

240

Read Data Setup PIOA

SUA

500

Read Data Setup PIOB

SUB

500

Delay to Program

Delay to Verify

Program Pulse Width

480

Program Voltage Rise Time

0.5

5.0

Program Voltage Fall Time

0.5

5.0

DEFINITION OF PIO READ DATA SETUP TIME

DS2407

012099 31/31

PIO SINK CURRENT

ÍÍÍÍÍÍÍÍÍÍÍ

2.8V

PUP

100 mA

90 mA

80 mA

70 mA

60 mA

50 mA

40 mA

30 mA

20 mA

10 mA

MAX.

MIN.

MAX.

MIN.

, I

@ 0.4V

PIOA

PIOB

NOTES:

1. All voltages are referenced to ground.
2. V

PUP

, V

PUPA

, V

PUPB

= external pullup voltage.

3. Input load is to ground.
4. An additional reset or communication sequence cannot begin until the reset high time has expired.
5. Read data setup time refers to the time the host must pull the 1Wire bus low to read a bit. Data is guaranteed

to be valid within 1

s of this falling edge and will remain valid for 14

s minimum (15

s total from falling edge

on 1Wire bus).

6. V

is a function of the chipinternal supply voltage. This voltage is determined by either the external pullup resis-

tor and V

PUP

or the V

supply, whichever is higher.

7. Capacitance on the data pin could be 800 pF when power is first applied. If a 5k

resistor is used to pull up the

data line to V

PUP

, 5

s after power has been applied the parasite capacitance will not affect normal communica-

tions.

8. t

RSTL

should be limited to maximum 5 ms. Otherwise the DS2407 may perform a poweron reset.

9. Input resistance is to ground.
10. V

must be at least 4.0V if it is to be connected during a programming pulse.

11. If the current at PIOA reaches 200 mA the gate voltage of the output transistor will be reduced to limit the sink

current to 200 mA. The usersupplied circuitry should limit the current flow through the PIOtransistor to no more
than 100 mA. Otherwise the DS2407 may be damaged.

12. PIOA has a controlled turnon output. The indicated currents are DC values. At V

PUP

= 4.0V or higher the sink

current typically reaches 80% of its DC value 1

s after turning on the transistor.

13. Under certain low voltage conditions V

ILMAX

may have to be reduced to as much as 0.5V to always guarantee

a presence pulse.

14. The input load current may be as high as 100

A after a poweron reset until a memory function command byte

has been sent as well as during the execution of a ROM function command.

15. If the device is disconnected from the 1Wire bus (data pin floating) channel A may lose its output status even

if V

is connected. A resistor of approximately 100 k

between V

and data will maintain the status of

channel A.

16. Without V

supply, V

for either PIO pin should always be greater than or equal to V

PUP

0.3V.

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