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REV: 070105
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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.
GENERAL DESCRIPTION
The DS26334 is a 16-channel short/long-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A single bill of material can
support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high impedance
modes and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered. The device is offered in a 256-pin
TEBGA, the smallest package available for a 16-
channel LIU.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
TNEG
RCLK
TPOS
TCLK
RPOS
RNEG
SOFTWARE CONTROL
AND JTAG
TRANSMITTER
RECEIVER
LOSS
1
16
RTIP
RRING
MODE
JTAG
TTIP
TRING
FEATURES
16 E1, T1, or J1 Short/Long-Haul Line Interface
Units
Independent E1, T1 or J1 Selections
Software-Selectable Transmit and Receive-Side
Impedance Matching
Crystal Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode and
AMI or HDB3/ B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss of Signal Detection as per
T1.231, G.775 and ETSI 300233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation. This Clock will be Internally Adapted
for T1 or E1 Usage.
Receiver Signal Level Indicator from -2.5dB to
-38dB in T1 Mode and 3dB to 43dB in E1
Mode in 2.5dB Increments
Two Built-In BERT Testers for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Transmit Short Circuit Protection
G.772 Nonintrusive Monitoring
Receive Monitor Mode Handles Combinations of
14dB to 30dB of Resistive Attenuation Along with
12dB to 30dB of Cable Attenuation
Specification Compliance to the Latest T1 and
E1 Standards--ANSI T1.102, AT&T Pub 62411,
T1.231, T1.403, ITU G.703, G.742, G.775,
G.823, ETSI 300 166, and ETSI 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as per IEEE 1149.1
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26334G
0C to +70C
256 TEBGA
DS26334GN
-40C to +85C 256 TEBGA
DS26334
3.3V, 16-Channel, E1/T1/J1 Short-
and Long-Haul Line Interface Unit
www.maxim-ic.com
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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TABLE OF CONTENTS
1 STANDARDS
COMPLIANCE ........................................................................................................ 6
1.1 T
ELECOM
S
PECIFICATIONS COMPLIANCE
....................................................................................... 6
2 DETAILED
DESCRIPTION ............................................................................................................ 7
3 BLOCK
DIAGRAMS ...................................................................................................................... 8
4 PIN
DESCRIPTION ...................................................................................................................... 10
5 FUNCTIONAL
DESCRIPTION ..................................................................................................... 18
5.1 P
ORT
O
PERATION
...................................................................................................................... 18
5.1.1 Serial Port Operation.............................................................................................................................. 18
5.1.2 Parallel Port Operation ........................................................................................................................... 19
5.1.3 Interrupt Handling................................................................................................................................... 19
5.2 P
OWER
-U
P AND
R
ESET
.............................................................................................................. 20
5.3 M
ASTER
C
LOCK
......................................................................................................................... 20
5.4 T
RANSMITTER
............................................................................................................................ 21
5.4.1 Transmit Line Templates........................................................................................................................ 23
5.4.2 LIU Transmit Front End .......................................................................................................................... 26
5.4.3 Dual Rail................................................................................................................................................. 27
5.4.4 Single-Rail Mode .................................................................................................................................... 27
5.4.5 Zero Suppression--B8ZS or HDB3 ....................................................................................................... 27
5.4.6 Transmit Power-Down............................................................................................................................ 27
5.4.7 Transmit All Ones................................................................................................................................... 28
5.4.8 Drive Failure Monitor .............................................................................................................................. 28
5.5 R
ECEIVER
.................................................................................................................................. 28
5.5.1 Receiver Monitor Mode .......................................................................................................................... 28
5.5.2 Peak Detector and Slicer ....................................................................................................................... 28
5.5.3 Receive Level Indicator .......................................................................................................................... 28
5.5.4 Clock and Data Recovery ...................................................................................................................... 29
5.5.5 Loss of Signal......................................................................................................................................... 29
5.5.6 AIS.......................................................................................................................................................... 30
5.5.7 Bipolar Violation and Excessive Zero Detector...................................................................................... 31
5.6 J
ITTER
A
TTENUATOR
.................................................................................................................. 31
5.7 G.772
M
ONITOR
........................................................................................................................ 32
5.8 L
OOPBACKS
............................................................................................................................... 32
5.8.1 Analog Loopback.................................................................................................................................... 32
5.8.2 Digital Loopback..................................................................................................................................... 33
5.8.3 Remote Loopback .................................................................................................................................. 34
5.9 BERT........................................................................................................................................ 34
5.9.1 General Description................................................................................................................................ 34
5.9.2 Configuration and Monitoring ................................................................................................................. 35
5.9.3 Receive Pattern Detection ..................................................................................................................... 36
5.9.4 Transmit Pattern Generation.................................................................................................................. 38
6 REGISTER
MAPS
AND
DEFINITION .......................................................................................... 39
6.1 R
EGISTER
D
ESCRIPTION
............................................................................................................. 48
6.1.1 Primary Register Bank ........................................................................................................................... 48
6.1.2 Secondary Register Bank ...................................................................................................................... 61
6.1.3 Individual LIU Register Bank.................................................................................................................. 64
6.1.4 BERT Registers...................................................................................................................................... 81
7
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ................................. 88
7.1 TAP
C
ONTROLLER
S
TATE
M
ACHINE
............................................................................................ 89
7.2 I
NSTRUCTION
R
EGISTER
............................................................................................................. 92
7.3 T
EST
R
EGISTERS
....................................................................................................................... 93
7.4 B
OUNDARY
S
CAN
R
EGISTER
....................................................................................................... 93
7.5 B
YPASS
R
EGISTER
..................................................................................................................... 93
7.6 I
DENTIFICATION
R
EGISTER
.......................................................................................................... 93
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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8
DC ELECTRICAL CHARACTERIZATION ................................................................................... 94
9 AC
TIMING
CHARACTERISTICS ................................................................................................ 95
9.1 L
INE
I
NTERFACE
C
HARACTERISTICS
............................................................................................ 95
9.2 P
ARALLEL
H
OST
I
NTERFACE
T
IMING
C
HARACTERISTICS
............................................................... 96
9.3 S
ERIAL
P
ORT
........................................................................................................................... 108
9.4 S
YSTEM
T
IMING
....................................................................................................................... 109
9.5 JTAG
T
IMING
.......................................................................................................................... 111
10 PIN
ASSIGNMENT..................................................................................................................... 112
11 PACKAGE
INFORMATION........................................................................................................ 113
12 THERMAL
INFORMATION ........................................................................................................ 114
13 REVISION
HISTORY.................................................................................................................. 115
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 3-2. Receive Logic Detail.................................................................................................................................. 9
Figure 3-3. Transmit Logic Detail................................................................................................................................. 9
Figure 5-1. Serial Port Operation for Write Access ................................................................................................... 18
Figure 5-2. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 18
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 19
Figure 5-4. Interrupt Handling Flow Diagram ............................................................................................................ 20
Figure 5-5. Pre-Scaler PLL and Clock Generator...................................................................................................... 21
Figure 5-6. T1 Transmit Pulse Templates ................................................................................................................. 24
Figure 5-7. E1 Transmit Pulse Templates ................................................................................................................. 25
Figure 5-8. LIU Front End .......................................................................................................................................... 26
Figure 5-9. Jitter Attenuation ..................................................................................................................................... 32
Figure 5-10. Analog Loopback................................................................................................................................... 33
Figure 5-11 Digital Loopback..................................................................................................................................... 33
Figure 5-12. Remote Loopback ................................................................................................................................. 34
Figure 5-13. PRBS Synchronization State Diagram.................................................................................................. 36
Figure 5-14. Repetitive Pattern Synchronization State Diagram............................................................................... 37
Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 88
Figure 7-2. TAP Controller State Diagram................................................................................................................. 91
Figure 9-1. Intel Nonmuxed Read Cycle ................................................................................................................... 97
Figure 9-2. Intel Mux Read Cycle .............................................................................................................................. 98
Figure 9-3. Intel Nonmux Write Cycle...................................................................................................................... 100
Figure 9-4. Intel Mux Write Cycle ............................................................................................................................ 101
Figure 9-5. Motorola Nonmux Read Cycle .............................................................................................................. 103
Figure 9-6. Motorola Mux Read Cycle ..................................................................................................................... 104
Figure 9-7. Motorola Nonmux Write Cycle .............................................................................................................. 106
Figure 9-8. Motorola Mux Write Cycle ..................................................................................................................... 107
Figure 9-9. Serial Bus Timing Write Operation........................................................................................................ 108
Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 108
Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 108
Figure 9-12. Transmitter Systems Timing................................................................................................................ 109
Figure 9-13. Receiver Systems Timing ................................................................................................................... 110
Figure 9-14. JTAG Timing ....................................................................................................................................... 111
Figure 10-1. 256-Ball TEBGA .................................................................................................................................. 112
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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LIST OF TABLES
Table 4-1. Pin Descriptions........................................................................................................................................ 10
Table 5-1. Parallel Port Mode Selection and Pin Functions ...................................................................................... 19
Table 5-2. Telecommunications Specification Compliance for DS26334 Transmitters ............................................ 22
Table 5-3. Registers Related to Control of DS26334 Transmitters ........................................................................... 22
Table 5-4. Template Selections for Short-Haul Mode ............................................................................................... 23
Table 5-5. Template Selections for Long-Haul Mode ................................................................................................ 23
Table 5-6. LIU Front-End Values ............................................................................................................................... 27
Table 5-7. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications............................................................... 29
Table 5-8. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications................................................................. 30
Table 5-9. AIS Detection and Reset Criteria for DS26334 ........................................................................................ 30
Table 5-10. Registers Related to AIS Detection........................................................................................................ 30
Table 5-11. BPV, Code Violation, and Excessive Zero Error Reporting ................................................................... 31
Table 5-12. Pseudorandom Pattern Generation........................................................................................................ 35
Table 5-13. Repetitive Pattern Generation ................................................................................................................ 35
Table 6-1. Primary Register Set ................................................................................................................................ 40
Table 6-2. Secondary Register Set............................................................................................................................ 41
Table 6-3. Individual LIU Register Set ....................................................................................................................... 42
Table 6-4. BERT Register Set ................................................................................................................................... 43
Table 6-5. Primary Register Set Bit Map ................................................................................................................... 44
Table 6-6. Secondary Register Set Bit Map .............................................................................................................. 45
Table 6-7. Individual LIU Register Set Bit Map.......................................................................................................... 46
Table 6-8. BERT Register Bit Map ............................................................................................................................ 47
Table 6-9. G.772 Monitoring Control (LIU 1) ............................................................................................................. 53
Table 6-10. G.772 Monitoring Control (LIU 9) ........................................................................................................... 53
Table 6-12. TST Template Select Transmitter Register ............................................................................................ 57
Table 6-13. TST Template Select Transmitter Register ............................................................................................ 57
Table 6-14. Template Selection................................................................................................................................. 58
Table 6-15. Address Pointer Bank Selection............................................................................................................. 61
Table 6-16. DS26334 MCLK Selections .................................................................................................................... 67
Table 6-17. Receiver Sensitivity/Monitor Mode Gain Selection ................................................................................ 72
Table 6-18. Receiver Signal Level............................................................................................................................. 73
Table 6-19. Bit Error Rate Transceiver Select for Channels 18 .............................................................................. 76
Table 6-20. Bit Error Rate Transceiver Select for Channels 916 ............................................................................ 76
Table 6-21. PLL Clock Select .................................................................................................................................... 78
Table 6-22. Clock A Select ........................................................................................................................................ 79
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 92
Table 7-2. ID Code Structure..................................................................................................................................... 93
Table 7-3. Device ID Codes....................................................................................................................................... 93
Table 8-1. DC Pin Logic Levels ................................................................................................................................. 94
Table 8-2. Pin Capacitance ....................................................................................................................................... 94
Table 8-3. Supply Current and Output Voltage ......................................................................................................... 94
Table 9-1. Transmitter Characteristics....................................................................................................................... 95
Table 9-2. Receiver Characteristics........................................................................................................................... 95
Table 9-3. Intel Read Mode Characteristics .............................................................................................................. 96
Table 9-4. Intel Write Cycle Characteristics .............................................................................................................. 99
Table 9-5. Motorola Read Cycle Characteristics ..................................................................................................... 102
Table 9-6. Motorola Write Cycle Characteristics ..................................................................................................... 105
Table 9-7. Serial Port Timing Characteristics .......................................................................................................... 108
Table 9-8. Transmitter System Timing..................................................................................................................... 109
Table 9-9. Receiver System Timing......................................................................................................................... 109
Table 9-10. JTAG Timing Characteristics................................................................................................................ 111
Table 12-1. Thermal Characteristics........................................................................................................................ 114
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