PIN
FUNCTION
PIN
FUNCTION
1
OUTPUT ENABLE (OE)
24
DGND
2
DGND
23
REF. BOTTOM (V
RB
)
3
BIT 8 (LSB)
22
SELF BIAS 1 (V
RBS
)
4
BIT 7
21
AGND
5
BIT 6
20
AGND
6
BIT 5
19
ANALOG INPUT (V
IN
)
7
BIT 4
18
+AV
S
(+5V)
8
BIT 3
17
REFERENCE TOP (V
R
T
)
9
BIT 2
16
SELF BIAS 2 (V
RTS
)
10
BIT 1 (MSB)
15
+AV
S
(+5V)
11
+DV
S
(+5V)
14
+AV
S
(+5V)
12
CLOCK INPUT (A/D CLK)
13
+DV
S
(+5V)
FEATURES
8-bit resolution, 20MHz min. sampling rate
LSB max. differential nonlinearity error
18MHz input signal bandwidth
Subranging, S&H enclosed
+5V single power, low 85mW max. dissipation
CMOS compatible logic input
3-State TTL compatible output
Figure 1. Functional Block Diagram
INPUT/OUTPUT CONNECTIONS
ADC-305
8-Bit, 20MHz
CMOS A/D Converters
Both the ADC-305-1 and the ADC-305-3 have the same pin assignment.
GENERAL DESCRIPTION
DATEL's ADC-305 is an 8-bit, 20MHz sampling, CMOS,
subranging (two-pass) A/D converter. It processes signals at
speeds comparable to a full flash converter by using a sub-
ranging conversion technique with multiple comparator blocks,
each containing a sample and hold amplifier.
The ADC-305 features CMOS low power dissipation (60mW
typical) and a wide 18MHz (1dB) input signal bandwidth.
The ADC-305-1 is packaged in 400 mil 24-pin DIP and the
ADC-305-3 in 300 mil 24-pin SOP.
Other features are CMOS compatible input logic, 3-state TTL
compatible output logic, +5V single power operation, self bias
mode and low cost.
DATEL, Inc., Mansfield, MA 02048-1151 (USA)
Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356
Email: sales@datel.com
Internet www.datel.com
UPPER
ENCODER
(4 BIT)
24 DGND
OUTPUT ENABLE 1
A/D CLK 12
BIT 8 (LSB) 3
BIT 1 (MSB) 10
BIT 7 4
23 V
RB
21 AGND
20 AGND
19 V
IN
15 +AV
S
14 +AV
S
13 +DV
S
18 +AV
S
17 V
RT
22 V
RBS
16 V
RTS
REFERENCE
VOLTAGE
B BLOCK
COMPARATORS
WITH S/H (4 BIT)
UPPER
COMPARATORS
WITH S/H (4 BIT)
LOWER
ENCODER
(4 BIT)
LOWER
ENCODER
(4 BIT)
CLOCK
GENERATOR
UPPER
DATA
LATCHES
LOWER
DATA
LATCHES
A BLOCK
COMPARATORS
WITH S/H (4 BIT)
DGND 2
+DV
S
11
BIT 6 5
BIT 5 6
BIT 4 7
BIT 3 8
BIT 2 9
ADC-305
TECHNICAL NOTES
1. The ADC-305 has separate +AV
S
and +DV
S
pins. It is
recommended that both +AV
S
and +DV
S
be powered from a
single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits
must be powered from a separate digital supply. +DV
S
(pins
11 and 13) and +AVs (pins 14, 15 and 18) should be tied
together externally. DGND (pins 2 and 24) and AGND (pins
20 and 21) should also be tied together externally. Power
supply grounds must be connected at one point to the
ground plane directly beneath the device. Digital returns
should not flow through analog grounds.
2. Bypass all power lines to ground with a 0.1F ceramic chip
capacitor in parallel with a 47F electrolytic capacitor.
Locate the bypass capacitor as close to the unit as
possible.
3. Even though the analog input capacitance is a low 15pF, it
is recommended that high frequency input be provided via
a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm
resister inserted between the output of an amplifier and the
analog input of the ADC-305 will improve the situation. A
resistor larger than 100 ohms may degrade linearity.
4. The input voltage range is determined by voltages applied
to V
RB
(Reference Bottom) and V
RT
(Reference Top). Keep
to the following equations;
0V
V
RB
V
RT
2.8V
1.8V
V
RT
V
RB
2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a. Tie V
RB
to V
RBS
, and tie V
RT
to V
RTS
respectively. The analog
input range in this case is +0.64V to +2.73V nominal.
b. Tie V
RB
to AGND, and tie V
RT
to V
RTS
respectively. The
analog input voltage range is 0 to +2.39V in this case.
FUNCTIONAL SPECIFICATIONS
(Specification are typical at T
A
= +25C, +V
RT
= +2.5V, V
RB
= +0.5V, +AV
S
= +DV
S
=
+5v, f
S
= 20MHz sampling unless otherwise specified.)
ANALOG INPUTS
MIN.
TYP.
MAX.
UNITS
Input Voltage Range (V
IN
)
--
+0.5 to +2.5
--
Volts
Input Capacitance
--
11
--
pF
(V
IN
= 1.5Vdc+0.07V
RMS
)
Input Impedance
--
12.5
--
k
Input Signal Bandwidth
--
18
--
MHz
(V
IN
-2Vp-p, 1dB)
REFERENCE INPUTS
Ref. Resitance
V
RT
to V
RB
230
300
450
Ref. Current
4.5
6.6
8.7
mA
Ref. Voltage
V
RT
+1.8
--
+2.8
Volts
V
RB
0
--
V
RT
Volts
Offset Voltage
V
RT
10
35
60
mV
V
RB
0
+15
+45
mV
Self Bias I V
RBS
+0.6
+0.64
+0.68
Volts
V
RTS
-V
RBS
+1.96
+2.09
+2.21
Volts
Self Bias II V
RTS
+2.25
+2.39
+2.53
Volts
DIGITAL INPUTS
Input Voltage (CMOS)
Logic Levels (V
IH
) "1"
+4
--
--
Volts
Logic Level (V
IL
) "0"
--
--
+1
Volts
Input Current (@V
IH
=+DV
S
)"1"
--
--
5
A
(@V
IL
=0) "0"
--
--
5
A
Clock Pulse Width T
PW1
25
--
--
ns
(A/D CLK)
T
PW0
25
--
--
ns
DIGITAL OUTPUTS
Output Data
8-bit Binary Parallel
Output Voltage
3-State TTL compatible
Output Current
Logic Level "1"
1.1
--
--
mA
Logic Level "0"
+3.7
--
--
mA
Output Current
Logic Level "1"
--
--
16
A
Logic Level "0"
--
--
16
A
Output Data Delay, Td
--
18
30
ns
PERFORMANCE
Resolution
8
--
--
Bit
Maximum Sampling Rate
20
--
--
MHz
Minimum Sampling Rate
--
--
0.5
MHz
Aperature Delay, T
A
--
4
--
ns
Aperature Jitter
--
30
--
ps
Differential Linearity Error
--
0.3
0.5
LSB
Integral Linearity Error
--
+0.5
+1.3
LSB
Differential Gain Error
--
1
--
%
Differential Phase Error
--
0.5
--
deg
POWER REQUIREMENTS
MIN.
TYP.
MAX.
UNITS
Power Supply (+AV
S
, +DV
S
)
+4.75
+5.0
+5.25
Volts
I A GND - D GND I
--
--
100
mV
Power Supply Current
--
12
17
mA
Power Dissipation
--
60
85
mW
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range
40 to +85C
Storage Temp. Range
55 to +150C
Package Type
ADC-305-1
24-pin Plastic DIP
ADC-305-3
24-pin Plastic SOP
Weight
ADC-305-1
2.0 grams
ADC-305-3
0.3 grams
Footnotes:
See Technical Note 4
Short V
RB
(pin 23) to V
RBS
(pin 22).
Short V
RT
(pin 17) to V
RTS
(pin 16).
Short V
RB
(pin 23) to A GND.
Short V
RT
(pin 17) to V
RTS
(pin 16).
2
OE=OV, V
OH
=+DV
S
0.5V,
V
OL
=+0.4V
OE=+DV
S
, V
OH
=+DV
S
, V
OL
=0V
NTSC 40IRE mode ramp, 14.3MHz
sampling
Table 1. Digital Output Coding
PARAMETERS
MIN
MAX
UNITS
Power Supply Voltage (+AV
S
, +DV
S
)
0.5
+7
Volts
Analog Input Voltage (V
IN
)
0.5
+AV
S
+0.5
Volts
Reference Input Voltage (V
RT
, V
RB
)
0.5
+AV
S
+0.5
Volts
Digital Input Voltage (V
IH
, V
IL
)
0.5
+DV
S
+0.5
Volts
Digital Output Voltage (V
OH
, V
OL
)
0.5
+DV
S
+0.5
Volts
ABSOLUTE MAXIMUM RATINGS (T
A
= 25C)
STEP
DATA BITS OUT
V
IN
CODE
DEC
HEX
MSB
LSB
O
V
Zero
0
00
0 0 0 0
0 0 0 0
+0.9922V
+1/2FS 1LSB
127
7F
0 1 1 1
1 1 1 1
+1.000V
+1/2FS
128
80
1 0 0 0
0 0 0 0
+1.9922V
+FS
255
FF
1 1 1 1
1 1 1 1
ADC-305
Figure 3. Equivalent Circuits
Figure 2. Timing Diagram
3
These values may differ from one device to another. Voltage
changes on the +5V supply have a direct influence on the
performance of the device. The use of external references is
recommended for applications sensitive to gain error.
External Reference Mode
Tie V
RB
to AGND, and apply +2V to V
RT
to use at 0 to +2V
input voltage range. The reference resistance between V
RB
and V
RT
is about 300 ohms. It is important to make the
output impedance of the reference source small enough
while, at the same time, keeping sufficient drive capacity.
Insert a 0.1F bypass ceramic chip capacitor between V
RT
and GND to minimize the effect of the 20MHz clock
running nearby. See Figure 5.
5. Logic inputs are CMOS compatible. Normally a series 74HC
is used as a driver. It is recommended to pull up to +5V if
the device is driven with TTL.
6. The start convert (A/D CLK) pulse can be a 50% duty cycle
clock. Both T
PW1
and T
PW0
are 25ns minimum. A slightly
longer T
PW1
will improve linearity of the system for higher
frequency input signals.
7. The digital data outputs are 3-state and TTL compatible. To
enable the 3-state outputs, connect the OUTPUT ENABLE
(pin 1) to GND. To disable, connect it to +5V. It is
recommended that the data outputs be latched and buffered
through output registers.
8. Maximum 30ns (18ns typical) after the rising edge of the
Nth conversion pulse, the result of the (N-3) conversion can
be obtained. Data is stored firmly in an output register, such
as an 74LS574, using the rising edge of a start convert
pulse as a trigger. The (N4) data is stored in this case. See
the timing diagrams, Figure 2 and 4.
9. The 20MHz sampling rate is guaranteed. It is not
recommended to use this device at sampling rates slower
than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit
required to maintain the specified accuracy of the device.
Ta
T
PW1
T
PW0
N
N+1
N+2
N+3
N+4
N
N+1
N-1
N-2
N-3
ANALOG
INPUT
CLOCK
DATA
OUTPUT
Td= 30ns max.
22
23
17
16
+DV
S
Digital Output Circuit, Bit1 through Bit 8
Analog Input
Generates +0.6V
when shorted with V
B
Generates +2.6V
when shorted with V
T
19
Voltage Reference (V
RT
,V
RB
)
Equivalent Circuit
Equivalent Circuit for OE and A/D CLK
OE - Low data is output when high digital
output pins turn to high impedance.
+AV
S
V
RBS
V
RTS
+DGND
OE
A/D CLK
+AV
S
V
IN
AGND
+AV
S
AGND
V
RT
V
RB
AGND
+DV
S
DGND
ADC-305
Figure 4. Timing Chart
ADC-305
4
ANALOG INPUT
(V
IN
)
A/D CLK
UPPER
SAMPLING
COMPARATOR
BLOCK
UPPER
OUTPUT
DATA
LOWER
REFERENCE
VOLTAGE
LOWER DATA A
LOWER
OUTPUT
DATA B
OUTPUT
DATA
S(1)
H(1)
C(1)
S(3)
C(3)
MD(N-1)
MD(N)
MD(N+1)
MD(N+2)
RV(N-1)
RV(N)
RV(N+1)
RV(N+2)
S(N)
C(N)
C(N+1)
S(N+2)
C(N+2)
S(N+3)
C(N+3)
H(3)
S(N+1)
LD(N-2)
LD(N)
H(0-1)
C(N-1)
S(N+1)
H(N+1)
S(N+3)
C(N+1)
H(N+3)
LD(N-3)
LD(N-1)
LD(N+1)
N-3
N-2
N-1
N
N
N+1
N+2
N+3
LOWER
SAMPLING
COMPARATOR
A BLOCK
LOWER
SAMPLING
COMPARATOR
B BLOCK
ADC-305
Figure 5. Typical Connection Diagram
Figure 6. Typical Performance Curves
5
12
11
10
9
V
IN
(R
IN
= 75
)
100
Gain
Adjust
470F
120
51
680
5V(A)
510
V
RB
Adjust
2k
2SC2785
2SC2785
2SC2785
2.2k
Bias
Adjust
22F
10k
2.2k
2SC2785
+5V(A)
2k
510
510
47F
5V(A)
2SC2785
V
RT
Adjust
47F
+5V(A)
100H
0.1F
0.1F
0.1F
0.1F
75
0.1F
0.1F
0.1F
0.1F
24
23
22
21
20
19
18
17
16
15
14
13
ADC-305
8
7
6
5
4
3
2
1
0.1F
1
2
3
4
5
6
7
8
9
10
1
2
3
4
6
7
9
11
13
14
74HC04
75
Clock Input
(A/D CLK)
(R
IN
= 75
)
0.1F
0.1F
74LS574
11
12
13
14
15
16
17
18
19
20
+5V(D)
47F
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8 (LSB)
390
Supply Current vs. Sampling Rate
mA
20
15
10
S
u
p
p
l
y
C
u
r
r
e
n
t
5
10
15
20
25 30MHz
Sampling Rate
Supply Current vs. Sampling Voltage
mA
20
15
10
S
u
p
p
l
y
C
u
r
r
e
n
t
4.0
4.5
5.0
5.5V
Supply Voltage
5
Differential Linearity Error vs.
Input Signal Frequency
LSB
0.6
0.4
D
i
f
f
.
L
i
n
e
a
r
i
t
y
E
r
r
o
r
2
4
6
8
Input Signal Frequency
0.2
10MHz
+DVS=+AVS=+5V
FS = 20.48MHz
Ta=25C
+DVS=+AVS=+5V
VIN = 1kHz
Ta=25C
SNR + THD vs. Input Signal Frequency
dB
46
42
S
N
R
+
T
H
D
2
4
6
Input Signal Frequency
38
7MHz
+DVS=+AVS=+5V
FS = 20.48MHz
Ta=25C
36
1
3
5
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