DATEL, Inc., Mansfield, MA 02048 (U.S.A.)

Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356

Email: sales@datel.com

Internet: www.datel.com

ADS-230/ADS-231

Low-Power, 12-Bit, 1.0/1.5MHz

Sampling A/D Converter

FEATURES

12-bit resolution

1.0 and 1.5MHz throughput rates

Small 44-pin Leaded Chip Carrier

Single +5V supply

Low power, 75 and 200mW maximum

Low power "standby" mode

Outstanding dynamic performance

No missing codes over temperature

Built-in sample-and-hold

Optional two-channel input multiplexer

Ideal for both time and frequency-domain applications

GENERAL DESCRIPTION

The ADS-230 and ADS-231 are 12-bit, high speed CMOS
sampling analog-to-digital converters capable of minimum

sampling rates of 1.0 and 1.5MHz, respectively. Both models

feature excellent dynamic performance including a typical
SNR of 72dB for the ADS-230 and 70dB for the ADS-231.

The ADS-230 and ADS-231 are packaged in a small 44-pin

plastic Leaded Chip Carrier (LCC). Each model contains a
fast-settling sample/hold amplifier, a multipass (three-step

flash) A/D converter, timing and control logic, three-state

outputs, a two-channel multiplexer, and digital error correction
circuitry. Digital input and output levels are TTL.

Requiring only a single +5V supply, the ADS-230 typically

dissipates only 60mW and the ADS-231 only 170mW. Both
models offer a low-power "standby" mode resulting in typical

power dissipations of 100µW and 250µW, respectively. The

units offer a maximum unipolar input range of 0 to +5V. The
exact value of the input range is determined by an externally

applied reference voltage. Both models operate over the

extended 40 to +85°C temperature range.

Figure 1. ADS-220/-231 Simplified Block Diagram

AGND

BIT 1 (MSB)

BIT 2

R/16

BIT 3

BIT 4

BIT 5

CH1

BIT 6

BIT 7

CH2

BIT 8

BIT 9

MUX OUT

ANALOG INPUT

BIT 10

AGND

BIT 11

BIT 12 (LSB)

DGND C

EOC

SEL

INT

DGND C

DGND D

DGND C

TEST

S/H

INPUT/OUTPUT CONNECTIONS

PIN

FUNCTION

PIN

FUNCTION

SAMPLE

AND HOLD

12-BIT A/D CONVERTER

OUTPUT LATCH

AND

THREE-STATE

BUFFER

TIMING AND CONTROL CIRCUITRY

MULTIPLEXER

ANALOG INPUT 12

MUX OUT

CH1

CH2

14,44

R/16

26,18,15

1,13

SEL

DGND C

DGND D

AGND

TEST

S/H

EOC

INT

PIN
43 BIT 1 (MSB)
42 BIT 2
41 BIT 3
40 BIT 4
39 BIT 5
38 BIT 6
37 BIT 7
36 BIT 8
35 BIT 9
33 BIT 10
32 BIT 11
31 BIT 12 (LSB)

ADS-230/ADS-231

ADS-230

ADS-231

+25°C

40 to +85°C

+25°C

40 to +85°C

ANALOG INPUT

TYP.

MIN.

MAX.

TYP.

MIN.

MAX.

UNITS

Input Voltage Range (Pins 7, 9, 12)

0.05

+0.05

0.05

+0.05

Input Leakage Current

0.1

µA

Input Capacitance

MUX On/Off-Channel Leakage

0.1

µA

MUX Input Capacitance

MUX Off-Channel Isolation

= 100kHz, 0dB

REFERENCE INPUT

Reference Input + (Pin 6), V

Reference Input (Pin 2), V

Reference Resistance

750

500

1000

750

500

1000

Ohms

DIGITAL INPUT

Logic Levels

Logic "1", V

= 5.5V

Logic "0", V

= 4.5V

0.8

Logic Loading "1"

0.1

µA

Logic Loading "0"

0.1

µA

Digital Input Capacitance

S/H Pulse Width , t

S/H

550

400

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

±0.4

±1.5

±0.4

±1.5

LSB

Differential Nonlinearity Error

±0.4

±0.95

±0.4

±0.95

LSB

No Missing Codes

Bits

Offset Error

±0.3

±2.0

±0.3

±2.0

LSB

Gain Error

±0.2

±1.5

±0.3

±1.5

LSB

Power Supply Sensitivity, (±10%)

±1.0

±0.75

LSB

DYNAMIC PERFORMANCE

Total Harmonic Distortion (0dB)

= 100kHz

Signal-to-Noise Ratio

(wo/distortion, 0dB) F

= 100kHz

69.5

67.5

Signal-to-Noise Ratio

(& distortion, 0dB) F

= 100kHz

Two-Tone Intermodulation Distortion

= 102.3, 102.7kHz, (0dB)

Aperature Delay Time, (t

)

A/D Conversion Rate

1.5

MHz

PARAMETERS

LIMITS

UNITS

Supply Voltages

= AV

= DV

)

0.3 to +6

Input or Output Voltage, any pin

0.3 to V

+0.3

Input Current, any pin

Total Package Input Current,

Power Dissipation,

875

ESD Susceptibilty,

2000

Soldering, Infrared, 15 seconds

+300

°C

ABSOLUTE MAXIMUM RATINGS

FUNCTIONAL SPECIFICATIONS

(The following specifications apply for T

= T

= 25°C, DV

= AV

= 5.0V, V

= +4.096V, V

= AGND, R

= 25ohms and F

= 1.0/1.5MHz for the ADS-230/231 respectively, unless

otherwise specified.)

PHYSICAL/ENVIRONMENTAL

PARAMETERS

MIN.

TYP.

MAX.

UNITS

Operating Temp. Range T

= T

+85

°C

Thermal Impedance,

°C/Watt

Maximum Junction Temp. T

JMAX

+150

°C

Storage Temperature Range

+150

°C

Package Type

44-pin Plastic Leaded Chip Carrier

ADS-230/ADS-231

ADS-230

ADS-231

+25°C

40 to +85°C

+25°C

40 to +85°C

TIMING

TYP.

MIN.

MAX.

TYP.

MIN.

MAX.

UNITS

Conversion Time, t

CONV

740

600

980

580

510

660

Time for Conversion to Start, t

EOC

125

Access Time, t

ACC

= 100pF)

Three-State Control Time, t1H, t0H

= 1k, C

= 10pF

Delay Time, RD Low to INT High

INTH

, C

= 100pF

Delay Time, EOC High to INT Low

INTL

, C

= 100pF

EOC High to Data Valid, t

UPDATE

MUX Address Setup Time, t

MUX Address Hold Time, t

CS Setup Time, t

CSS

CS Hold Time, t

CSH

Wake-up Time, t

PD High to First S/H Low

µs

DIGITAL OUTPUT

Logic Levels

Logic "1" (V

= 4.5V)

2.4

Logic "0", (V

= 4.5V)

0.4

Logic Loading "1"

360

µA

Logic Loading "0"

1.6

Three-State Output Leakage

0.1

µA

Three-State Output Capacitance

Output Coding

Binary

POWER REQUIREMENTS

Power Supply Range

+5V Supply, V

= AV

= DV

4.5

5.5

4.75

5.25

Power Supply Current

Supply Current, DI

Supply Current, AI

Standby Current (AI

+DI

, PD = 0)

µA

Power Dissipation

200

Footnotes:

When the input voltage at any pin exceeds the power supply rails (below

GND or Above V

) the input current must be limited to ±25mA or less. The

package input current limits to two the number of pins that can meet this

constant.

In most cases, the maximum derated power dissipation will be reached only

during fault conditions.

This is the ESD rating for the human body model, with a 100pF capacitor

discharged through a 1.5 kilohm resistor. The ESD rating for the machine

model is 200V.

For best performance, the rising edge of the S/H pulse must not be near

either the falling or rising edge of EOC. The recommended values of t

S/H

are:

ADS-230: 5ns<t

S/H

<40ns, or 150ns<t

S/H

<550ns

ADS-231: 5ns<t

S/H

<40ns, or 150ns<t

S/H

<400ns

The MUX inputs CH1

and CH2

are not used during dynamic testing of these

models. The internal multiplexer adds harmonic distortion at high input frequencies.

See the Typical Performance Curves for THD with and without the MUX.

The contributions from the first nine harmonics are used in the calculation of THD.

Effective bits is equal to:

(SNR + Distortion 1.76 + [20 log

Some units may have higher standby currents than the typical indicated. Production

testing of standby current is prohibitive due to the 10 second delay time on DI

after

PD is pulled low.

Full Scale Amplitude

Actual Input Amplitude

])

6.02

ADS-230/ADS-231

PIN DESCRIPTIONS

, DV

These are the analog and digital power supply input pins. They should all be connected to

the same voltage source. Both AV

pins should be bypassed to AGND and the DV

pin to

DGNDD. Bypass using a 0.1µF ceramic capacitor in parallel with a 10µF tantalum

capacitor.

AGND, DGNDC, DGNDD

These are the analog and digital ground pins. All of the ground pins should be returned to

the same potential and connected to a stable, noise-free system ground. AGND is the

analog ground. DGNDC is the ground for the digital control lines. DGNDD is the digital
ground for the output data bus.

BIT 1 BIT 12

These are the three-state data output pins. Output is enabled by RD, CS, and OE.

CH1

, CH2

These are the analog input pins to the internal input multiplexer.

MUX OUT

This is the output of the internal multiplexer,

ANALOG INPUT

This is the direct input to the sampling A to D converter.

SEL

This is the multiplexer channel select pin. The input is selected based on the state of SEL
when EOC transitions low. A low selects channel one and a high selects channel two. See

Table 1.

Connect to DGNDC

TEST

Connect to DV

This is the Chip Select control input. When low, this pin enables the RD, S/H and OE inputs.

This pin can be tied low.

INT

This is the Interrupt output pin. When using the Interrupt Interface Mode, this output goes

low when a conversion is completed and indicates that the data is available in the output
latches. This output is always high when RD is held low. Refer to the Timing Diagrams.

EOC

This is the End of Conversion output pin. EOC is low during a conversion.

This is the Read control input pin. When RD and CS are low, the INT output is reset and, if

EOC is high, data appears on the data bus. This pin can be tied low.

This is the Output Enable control input pin. The data output pins are in the high impedance

state when OE is low. Data appears when OE is high and CS and RD are both low. This pin

can be tied high.

S/H

This is the Sample and Hold control input pin. When CS is low a new conversion is initiated

by the falling edge of this input.

This is the Power Down control input pin. This pin is held high for normal operation. When

the input is low, the A to D converter goes into power standby mode.

R/16

Bypass this pin to AGND using a 0.1µF ceramic capacitor.

VT, VB

These are the positive (top) and negative (bottom) voltage reference force input pins,
respectively.

VTS, VBS

These are the positive (top) and negative (bottom) voltage reference sense pins,
respectively.

ADS-230/ADS-231

TECHNICAL NOTES

The Analog Input

For maximum performance, the source impedance driving the

input of the ADS-230/-231 should be as low as possible. A

source impedance of less than 100 ohms is recommended.
See the Typical Performance Curves.

If the signal source has high output impedance, the output

should be buffered with an op-amp capable of driving a
switched 25pF/100ohm load. Any ringing or instability of the

op-amp during the sampling period can cause conversion

errors.

Using a high-speed buffer also improves the THD

performance when using the internal MUX. The MUX on-

resistance is non-linear over the range of the input voltage;
this causes the RC time constant of the equivalent circuit

shown in Figure 2 to vary with input voltage. This results in

harmonic distortion with increasing frequency. Inserting a
buffer between the MUX OUT and ANALOG INPUT terminals

will eliminate the loading on R

MUX

and significantly reduce

THD.

The analog input of the ADS-230/-231 can be modeled as

shown in Figure 2. The S/H switch is closed during the sample

period, and open during hold. The hold capacitor (C

) has to

be charged to the input voltage by the source within the

sample period. The source impedance (R

) will directly effect

the charge time. If R

is too large, the voltage across C

will

not settle to within ½ LSB's of the source voltage before

conversion begins. This will result in conversion errors.

The combination of R

, R

MUX

, R

and C

form a low-pass

filter. Therefore, minimizing R

will increase the frequency

response of the converter.

The settling time to n bits is:

SETTLE

= (R

+ R

MUX

+ R

) * C

* n * In(2)

The bandwidth of the input circuit is:

F (3dB) = 1/[2 * 3.14 * (R

+ R

MUX

+ R

) * C

]

Internal Multiplexer

Both the ADS-230 and ADS-231 have an internal multiplexer
that is controlled by the logic level on the SEL pin when EOC

goes low. See the timing diagrams. The MUX setup and hold

times can be determined from the following:

MS(wrt S/H)

= t

EOC (min)

MS(wrt S/H)

= 5060

MS(wrt S/H)

= 10ns

MH(wrt S/H)

= t

+ t

EOC (max)

MH(wrt S/H)

= 50 +125

MH(wrt S/H)

= 175ns

Note that the 10ns indicates that data on SEL must be valid
within 10ns of the S/H pulse going low in order to meet the

setup time requirements. SEL must be valid for the length of

time determined by the following equation:

+ t

EOC(max)

) (t

EOC (min)

) = 185ns

Table 1. Internal Multiplexer Programming

SEL

Channel

CH1IN

CH2IN

Figure 3. Reference Force Input Only

Figure 2. ADS-230/-231 Input Stage Model

Table 1 shows the coding for MUX channel selection.

The output of the MUX is available at the MUX OUT pin. This
output allows the user to perform additional signal processing,

such as buffering, filtering or gain, before the signal is brought

to the ANALOG INPUT pin. If signal processing is not required
connect the MUX OUT pin directly to the ANALOG INPUT pin.

CH1

TO COMPARATORS

ADS-230/231

MUX

CH2

MUX OUT

ANALOG

INPUT

SOURCE

S/H

SWITCH

TYPICAL VALUES

MUX

= 100

= 25pF

4.096V

+5V ±5%

10µF

0.1µF

4.093V

R/16

0.1µF

REFERENCE

LADDER

ADS-230/231

0.003V

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS-231

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS-231