FEATURES

5MHz (ADS-235/236) and 9MHz (ADS-237) sampling rates

Low power

Outstanding dynamic performance

Fully differential or single-ended analog input

100MHz full power input bandwidth

Integral sample-and-hold

Single +5V supply operation

Internally generated DC bias Voltage

3.0/5.0V CMOS compatible digital output

TTL/CMOS compatible digital inputs/outputs

ADS-235, ADS-236, ADS-237

12-Bit, 5MHz and 9MHz

Sampling A/D Converters

GENERAL DESCRIPTION

The ADS-235, ADS-236 and ADS-237 are monolithic, 12-bit,
sampling analog-to-digital converters fabricated in a CMOS
process. The converters are designed for applications where
high speed, wide bandwidth and low power dissipation are
essential. These characteristics are provided through the use
of a fully differential sampling pipeline A/D architecture with
digital error correction logic.

The ADS-235, ADS-236 and ADS-237 offer excellent dynamic
performance while consuming only 300mW. The digital output
circuit is separate and can be powered from either a 3V or 5V
supply allowing the user to interface with 3V logic, if desired.

The ADS-235, ADS-236 and ADS-237 provide the user with
an internally generated DC bias voltage output. This DC bias
voltage is ideal for AC coupled analog input applications.
The units are available in a 28-lead plastic SOIC package
and operate over the 0°C to 70°C and 40 to +85°C
temperature ranges.

INPUT/OUTPUT CONNECTIONS

Figure 1. ADS-235, ADS-236 and ADS-237 Functional Block Diagram

PIN FUNCTION

DATEL, Inc., Mansfield, MA 02048 (USA)

Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356

Email: sales@datel.com

Internet:

www.datel.com

CLK, CLOCK

BIT 12

+DV

1, +5V DIG. SUP.

BIT 11

DGND1

BIT 10

+DV

1, +5V DIG. SUP.

BIT 9

DGND1

BIT 8

+AV

, +5V ANALOG SUP. 23

BIT 7

AGND

+DV

2, DIG. OUTPUT SUP.

+, ANALOG INPUT

DGND2

, ANALOG INPUT

BIT 6

, DC BIAS OUTPUT

BIT 5

ROUT

, REF. OUT

BIT 4

RIN

, REF. IN

BIT 3

AGND

BIT 2

+AV

, +5V ANALOG SUP. 15

BIT 1 (MSB)

Reference

4-Bit

Flash A/D

4-Bit
DAC

Stage 4

2.3 Volt

DC Bias Output

15 Bit 1 (MSB)

16 Bit 2

17 Bit 3

18 Bit 4

19 Bit 5

20 Bit 6

23 Bit 7

24 Bit 8

25 Bit 9

26 Bit 10

27 Bit 11

28 Bit 12 (LSB)

Digital Delay

and

Error

Correction

Clock

ROUT

RIN

1 CLK

2, 4

+DV

3, 5

DGND 1

6, 14
+AV

7, 13

AGND

+DV

DGND 2

Stage 3

4-Bit

Flash A/D

Stage 1

S/H

4-Bit

Flash A/D

ADS-235, ADS-236, ADS-237

Second Harmonic, F

=1MHz

ADS-235

ADS-236

ADS-237

Third Harmonic, F

=1MHz

ADS-235

ADS-236

ADS-237

Effective Number Of Bits,

ENOB, F

=1MHz

ADS-235

10.3

Bits

ADS-236

Bits

ADS-237

10.8

Bits

Signal to Noise Ratio and

Distortion, SINAD, F

=1MHz

ADS-235

ADS-236

ADS-237

66.5

Signal to Noise Ratio,

SNR, F

=1MHz

ADS-235

ADS-236

ADS-237

67.3

Intermodulation Distortion,

IMD, F1=1MHz F2=1.02MHz
ADS-235

ADS-236

ADS-237

Transient Response

Cycle

Over-Voltage Recovery,

0.2V Overdrive

Cycle

TIMING CHARACTERISTICS

Data Output Hold, t

Data Output Delay, t

Clock Pulse Width, TPWO, TPW1

ADS-235, ADS-236

100

110

ADS-237

106

111

116

Data Latency, t

LAT

Cycles

DC BIAS VOLTAGE OUTPUT

DC Bias Voltage Output,V

2.3

volts

DC Bias Voltage Current

1.0

DIGITAL OUTPUTS

Logic Levels

Logic "1", +DV

2=5V, V

=2.4V

0.2

Logic "0", +DV

2=5V, V

=0.4V

1.6

Logic "1", +DV

2=3V, V

=2.4V

0.2

Logic "0", +DV

2=3V, V

=0.4V

1.6

Output Capacitance

Max. Peak-to-Peak Diff. Voltage

Input Range (V

+ - V

)

±2.0

Volts

Max. Peak-to-Peak Single-Ended

Voltage Input Range

4.0

Volts

Analog Input Common Mode

Voltage Range (V

+ + V

)/2

1.0

2.3

4.0

Volts

Input Bias Current, IB+ or IB

µA

Differential Input

Current, (IB+ - IB)

±0.5

µA

Input Impedance

1.0

Input Capacitance

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage, V

ROUT

3.5

Volts

Reference Output Current

Reference Temperature Coefficient

ADS-235

ppm/°C

ADS-236

200

ppm/°C

ADS-237

ppm/°C

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

RIN

3.5

Volts

Total Reference Resistance, R

7.8

Reference Current

450

µA

PERFORMANCE

Resolution

Bits

Maximum Sample Rate, F

CLK

ADS-235

MHz

ADS-236

MHz

ADS-237

M H z

Minimum Sample Rate

0.5

M H z

Integral Nonlinearity, F

=DC

ADS-235

±2.0

LSB

ADS-236, ADS-237

±1.0

±2.0

LSB

Differential Nonlinearity,

=DC

±0.5

±1.0

LSB

Input Offset Error, F

=DC

ADS-235

LSB

ADS-236, ADS-237

LSB

Full Scale Error, F

=DC

ADS-235

LSB

ADS-236, ADS-237

LSB

Aperture Delay, t

Aperture Uncertainty, t

ps(RMS)

Full Power Input Bandwidth

100

MHz

Spurious Free Dynamic Range,
SFDR, F

=1MHz

ADS-235

ADS-236

ADS-237

Total Harmonic Distortion,

THD, F

=1MHz

ADS-235

ADS-236

ADS-237

ANALOG INPUTS

MIN.

TYP.

MAX.

UNITS

PARAMETERS

LIMITS

UNITS

PARAMETERS

MIN.

TYP.

MAX.

UNITS

ABSOLUTE MAXIMUM RATINGS

PHYSICAL/ENVIRONMENTAL

FUNCTIONAL SPECIFICATIONS

+AV

, +DV

1 and +DV

2 Supplies

+6.0

Volts

DGND to AGND

0.3

Volts

Analog I/O Pins

AGND to +AV

Supply

Volts

Digital I/O Pins

DGND to +DV

Supply

Volts

Lead Temperature
(10 seconds, Pin Tips Only)

300

°C

Operating Temperature Range

ADS-235S

°C

ADS-236S/ADS-237S

°C

Storage Temperature Range

150

°C

Thermal Resistance,

°C/W

Junction Temperature

150

°C

Package Type

= +25°C, (ADS-235), TMIN to TMAX (ADS-236/237), +DV

1 = +DV

2 = +AV

= +5V, V

RIN

= 3.5V, F

= 5MHz (ADS-235/236) and 9MHz (ADS-237) at a 50% duty

cycle, CL =10pF, and differential analog input unless otherwise specified.)

28-Pin Plastic SOIC

Measured mounted on PC board in free air.

PERFORMANCE (cont.)

MIN.

TYP.

MAX.

UNITS

ADS-235, ADS-236, ADS-237

Footnotes:

Differential Mode

CLK off and Low

Not specified

No missing codes

For F

step to settle to 12-bits accuracy

Power Supply Ranges

+5V Analog Supply, +AV

+4.75

+5.25

Volts

+5V Digital Supply, +DV

+4.75

+5.25

Volts

+3V Digital Supply, +DV

+2.7

+3.3

Volts

+5V Digital Supply, +DV

+4.75

+5.25

Volts

Power Supply Currents

ADS-235, ADS-236
+AI

+DI

ADS-237
+AI

+DI

Power Dissipation

ADS-235

300

ADS-236

300

350

ADS-237

325

365

Offset Error Sensitivity, 5V±5%

ADS-235

±16

LSB

ADS-236, ADS-237

LSB

Gain Error Sensitivity, 5V±5%

ADS-235

±16

LSB

ADS-236, ADS-237

LSB

POWER REQUIREMENTS

MIN.

TYP.

MAX.

UNITS

FUNCTIONAL DESCRIPTION

The ADS-235, ADS-236 and ADS-237 are 12-bit fully
differential pipeline sampling A/D converters with digital error
correction. Referring to the Functional Block Diagram shown in
figure 1, figure 3.1 shows the circuit for the front end differential
in and out sample-and-hold (S/H). The switches are controlled
by an internal sampling clock which is a non-overlapping two
phase signal, Ø1 and Ø2, derived from the master sampling
clock. During the sampling phase, Ø1, the input signal is

applied to the sampling capacitors, C

. At the same time the

hold capacitors, C

, are discharged to analog ground. At the

falling edge of Ø1 the input signal is sampled on the bottom
plates of the sampling capacitors. In the next clock phase, Ø2,
the two bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op-amp
output nodes. The charge then redistributes between C

and

completing one sample and hold cycle.

The sample and hold output is a fully differential representation
of the sampled analog input. The circuit not only performs the
sample-hold function but will also convert a single-ended input
to a fully differential output. During the sampling phase, the V

pins see only the on resistance of a switch and C

. The small

values of these components result in a typical full power input
bandwidth of 100MHz for the converters.

As illustrated in the Functional Block Diagram, figure 1, and the
Internal Timing Diagram, figure 2A, three identical pipeline
sub-converter stages, each containing a four-bit flash converter
and a four-bit multiplying digital-to-analog converter, follow the
S/H with the fourth stage being a four-bit flash converter. Each
converter stage in the pipeline will be sampling in one clock
phase and amplifying in the other clock phase. Each sub-
converter clock signal is offset by 180 degrees from the
previous stage clock signal resulting in alternate stages in the
pipeline performing the same operation.

The four-bit output of each of the sub-converter stages is used
by the error correction logic. The output of each stage is input
to a digital delay line which is controlled by the internal
sampling clock. The function of the delay line is to align the
digital outputs in time of the three identical stages with the
output of the fourth stage flash converter before applying the
sixteen bit result to the error correction logic. The error
correction logic uses the supplementary bits to correct any
error that may exist before generating the final twelve-bit digital
data output.

Due to the pipeline nature of this converter, the digital data
representing an analog input sample is output to the digital

Notes: 1. SN: N-th sampling period.

2. HN: N-th holding period.

3. BM, N: M-th stage digital output corresponding to N-th sampled input.

4. DN: Final data output corresponding to N-th sampled input.

Figure 2A. Internal Timing Diagram

Analog Input,

VIN

A/D CLK

1ST Stage

2ND Stage

4TH Stage

Data

Output

SN1 HN1

SN+1

SN+2

SN+3

tLAT

HN+1

HN+3

SN+4

HN+4

SN+5 HN+5 SN+6 HN+6

B1, N1

B1, N

B1, N+1

B2, N2

B2, N1

B2, N

B2, N+2

B2, N+3

B2, N+4

B4, N2

B4, N1

B4, N+1

B4, N+2

B4, N+3

B4, N+4

DN3

DN2

DN+1

DN+3

HN+2

B1, N1

B1, N

B1, N+1

B1, N+2

B1, N+3

B1, N+4

B1, N+5

3RD Stage

B3, N2

B3, N+1

B3, N+2

B3, N+3

B3, N+4

B3, N

B2, N+1

B2, N+5

B3, N1

B4, N

DN1

DN+2

ADS-235, ADS-236, ADS-237

Figure 2B. Input-to-Output Timing

Analog Input,

VIN

A/D CLK

Data

Output

tOD

tAJ

TPWO

TPW

8 n sec typ.

5 n sec typ.

5 p sec typ.

2.0V

0.5V

1.5V

tAP

data bus on the third cycle of the clock after the analog sample
is taken. After this latency delay, the digital data representing
each successive sample of the analog input is output during
the following clock cycle. The digital output data is
synchronized to the external sampling clock through a double
buffered latching circuit. The output of the digital error
correction circuit is available in offset binary format.

Differential Analog Input

The analog input is a differential input that can be configured in
various ways depending on the signal source and the level of
performance desired. A fully differential connection as shown
in figures 3.2 and 3.3 will give the best performance.

The ADS-235, ADS-236 and ADS-237 are powered by a single
+5V analog power supply which limits the analog input to
between ground and +5V. For the differential input connection
this implies that the analog input common mode voltage can
range from 1.0V to 4.0V, see figure 3.6. Performance for the
converter does not change significantly with the value of the
analog input common mode voltage. A DC voltage source, V

equal to 2.3V, typical, is provided to help simplify circuit design
when using an AC coupled differential input. This low
impedance voltage source is not designed to be a reference
voltage but makes an excellent DC bias source. This bias
voltage source stays well within the analog input common
mode voltage range over temperature.

The difference between the converter's two internal reference
voltages is 2V. For the AC coupled differential input, figure 3.2,
if V

is a 2Vp-p sinewave with V

180 degrees out of phase

with V

, then V

+ is a 2Vp-p sinewave riding on a DC bias

voltage equal to V

. Consequently, the converter will be at a

positive full scale when the V

+ input is at V

+1V and the

input is at V

-1V (V

+ - V

= 2V). Conversely, the ADS

will be at negative full scale when the V

+ input is equal to

-1V and V

is at V

+1V (V

+ - V

= 2V). Thus, the

converter has a peak-to-peak differential analog input voltage
range of ±2V.

The analog input can be DC coupled, figure 3.3, as long as the
inputs are within the analog input common mode voltage range
(1.0V

4.0V). The resistors, R, are not absolutely

necessary but may be used as load setting resistors. A
capacitor, C, connected from V

+ to V

will help filter high

frequency noise. Values of approximately 20pF are normally

sufficient but the actual value must take into account the
highest frequency component of the input signal.

Single-Ended Analog Input

The circuit in figure 3.4 may be used with a single-ended AC
coupled input. Assuming again that the difference between the
two internal voltage references is 2V and V

is a 4Vp-p

sinewave, then V

+ is a 4Vp-p sinewave riding on a positive

voltage equal to V

. The converter will be at a positive full

scale when V

+ is at V

+2V (V

+ - V

= 2V) and will be

equal to a negative full scale when VIN+ is equal toVDC-2V
(V

+ - V

= 2V). In this case, V

could range between 2V

and 3V without significant change in the converters
performance. The simplest way to obtain a V

voltage is to

use the V

output provided by the converters.

The single-ended analog input can be DC coupled, as shown
figure 3.5, as long as the input is within the analog input
common mode voltage range. The resistor, R, shown is not
absolutely necessary but may be used as a load setting
resistor. A capacitor, C, connected between V

+ and V

will

help filter high frequency noise. A value of approximately 20pF
is normally sufficient but the actual value must take into
account the highest frequency component of the input signal.

INTERNAL REFERENCE GENERATOR, VR

OUT

The ADS-235/236/237 have an internal reference generator,
therefore, an external voltage is not required. V

ROUT

must be

connected to V

RIN

when using the internal reference voltage.

Two reference voltages are generated internally, 1.3V and
3.3V, for a fully differential input range of ±2V.

An external reference may be used by connecting the external
voltage reference to the V

RIN

pin with V

ROUT

left open. These

units are tested with V

RIN

equal to 3.5V.

In order to minimize overall converter noise it is recommended
that adequate high frequency decoupling be provided at the
V

RIN

pin.

Digital I/O and Clock

The ADS-235, ADS-236 and ADS-237 provide a standard
high-speed interface to external TTL/CMOS logic families. In
order to ensure rated performance the duty cycle of the clock
should be held at 50% ±5%, have low jitter and operate at
standard TTL levels. Performance is guaranteed for conversion

ADS-235, ADS-236, ADS-237

rates above 0.5MHz in order to ensure proper performance of
the internal dynamic circuits.

Power Supplies and Grounding

The ADS-235, ADS-236 and ADS-237 have separate digital
and analog power supply pins and grounds (refer to the Input/
Output Connections table for pin numbers) to reduce digital
noise in the analog signal path. The digital data outputs also
have a separate supply pin, +DV

2, which can be powered

from either a 3.0V or 5.0V supply to allow the user the option
of interfacing with 3.0V logic.

The converters should be mounted on a board that provides
separate low impedance paths for the analog and digital

supplies and grounds. For best performance the supplies used
should be clean, linear regulated supplies. All power supplies
should be bypassed to ground with a 10uF tantalum capacitor
in parallel with a 0.1uF ceramic capacitor. Locate the bypass
capacitors as close to the converter as possible. If the converter
is to be powered from one supply then the analog supply and
ground pins should be isolated with ferrite beads from the
digital supply and ground pins. See the Typical Connection
Diagram, Figure 4.

In order to minimize overall converter noise it is recommended
that the V

RIN

pin be bypassed using a 4.7 uF tantalum capacitor

in parallel with a 0.01 uF ceramic capacitor. Locate the bypass
capacitors as close to the unit as possible.

Figure 3.1 Analog Input Sample-and-Hold

Figure 3.2 AC Coupled Differential Input

Figure 3.4 AC Coupled Single Ended Input

Figure 3.3 DC Coupled Differential Input

Figure 3.5 DC Coupled Single Ended Input

Figure 3.6 Differential Analog Input Common

Mode Voltage Range

Figure 3. Analog Input

OUT

Ø1

Ø2

+5V

on
M

de V

l
t
age

R
a

nge

2.0Vp-p

=+4.0V

=+1V

+1.0<V

<+4.0V

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS-235S