1 04-02-052D
Commercial/Industrial
PA7536 PEEL ArrayTM
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
High-Speed Commercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f
MAX
)
- Industrial grade available for 4.5 to 5.5V V
CC
and
-40 to +85 C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmer
General Description
The PA7536 is a member of the Programmable Electrically
Erasable Logic (PEELTM) Array family based on ICT's
CMOS EEPROM technology. PEELTM Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today's programmable logic designs. The PA7536 offers
versatile logic array architecture with 12 I/O pins, 14 input
pins and 36 registers/latches (12 buried logic cells, 12
Input registers/latches and 12 buried registers/latches). Its
logic array implements 50 sum-of-products logic functions
that share 64 product terms. The PA7536's logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a total of 36 for all 12 logic
cells). Cells are configurable as D, T, and JK registers with
independent or global clocks, resets, presets, clock
polarity, and other special features, making the PA7536
suitable for a variety of combinatorial, synchronous and
asynchronous logic applications. The PA7536 offers pin
compatibility and super-set functionality to popular 28-pin
PLDs, such as the 26V12. Thus, designs that exceed the
architectures of such devices can be expanded upon. The
PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
and 83.3MHz (f
MAX
) and moderate power consumption
60mA (45mA typical). Packaging includes 28-pin DIP,
SOIC, and PLCC (see Figure 1). Development and
programming support for the PA7536 is provided by ICT
and popular third-party development tool manufacturers.
Figure 1. Pin Configuration
08-16-001A
D IP
I/C LK1
1
I
2
I
3
I
4
I
5
I
6
VC C
7
I
8
I
9
I
10
I
11
I
12
I/O
24
I/O
23
I/O
22
G N D
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I
13
I
14
I/C LK2
28
I/O
27
I/O
26
I/O
25
1
I/C LK1
2
I
3
I
4
I
5
I
6
I
7
VC C
8
I
9
I
10
I
11
I
12
I
24
I/O
23
I/O
22
I/O
21
G N D
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
S O IC /TS S O P
13
I
14
I
28
I/C LK2
27
I/O
26
I/O
25
I/O
P L C C
25
I/O
24
I/O
23
I/O
22
I/O
21
G N D
20
I/O
19
I/O
4
I
3
I
2
I
1
I/
C
L
K
1
28
I/
C
L
K
2
27
I/
O
26
I/
O
5
I
6
I
7
VC C
8
I
9
I
10
I
11
I
12
I
13
I
14
I
15
I/
O
16
I/
O
17
I/
O
18
I/
O
Figure 2. Block Diagram
In pu t
Cells
(IN C )
1 2 In p ut P in s
2 Inp u t/
G lo ba l C lock Pins
G lo ba l
C e lls
2
1 2
I/O
C e lls
(IO C )
L og ic
C o ntro l
C e lls
(L C C )
1 2
1 2
1 2
1 2
A
B
C
D
7 6 (3 8 X 2)
A rra y In pu ts
true a n d
com ple m e n t
Buried
logic
2 su m te rm s
3 pro d uc t te rm s
for G lo b al C e lls
12 Lo gic C ontro l Cells
u p to 3 o u tp u t fu nction s p er c ell
(3 6 to tal o utp ut func tio n s po s sible)
L og ic fun ctio ns
to I/O ce lls
1 2 I/O Pins
4 8 s um te rm s
(fo ur p er LC C )
L og ic
Array
0 8-1 6-0 02 A
P A7536
I
I
I
I
I
VC C
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
G ND
I/CL K2
I/CL K1
I
I
I/O
I/O
I/O
G lo ba l Ce lls
In p ut C ells
I/O Ce lls
I
I/O
I/O
I/O
L og ic Co ntro l C e lls
2 04-02-052D
Commercial/Industrial
Inside the Logic Array
The heart of the PEELTM Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. Depending on the PEELTM Array selected, a
range of 38 to 62 inputs is available into the array from the
I/O cells, inputs cells and input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
number of product-terms among PEELTM Arrays ranges
from 67 to 125. All product terms (with the exception of
certain ones fed to the global cells) can be programmably
connected to any of the sum-terms of the logic control cells
(four sum-terms per logic control cell). Product-terms and
sum-terms are also routed to the global cells for control
purposes. Figure 3 shows a detailed view of the logic
array structure.
From
IO C ells
(IO C ,IN C ,
I/C LK)
From
Logic
C ontrol
C ells
(LC C )
To
G lobal
C ells
38 Array Inputs
67 Product T erm s
To
Logic C ontrol
C ells
(LC C )
50 Sum Term s
P A 75 36 L ogic A rray
0 8-1 6 -0 0 3A
Figure 3 PA7536 Logic Array
True Product-Term Sharing
The PEELTM logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can
be used for clocks, resets, presets and output enables
instead of just simple product-term control.
The PEELTM logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product
terms to implement 16 exclusive-OR functions. The
PEELTM logic array easily handles this in a single level
delay. Other PLDs/CPLDs either run out of product-terms
or require expanders or additional logic levels that often
slow performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control
the logic functions created in the logic array. Each LCC has
four primary inputs and three outputs. The inputs to each
LCC are complete sum-of-product logic functions from the
array, which can be used to implement combinatorial and
sequential logic functions, and to control LCC registers and
I/O cell output enables.
A
B
C
D
R E G
D ,T,J
K
R
P
Q
M U X
System Clock
Preset
Reset
O n/O ff
RegType
From G lobal C ell
M U X
M U X
To
Array
To
I/O
Cell
From
Array
08 -16-0 04A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with
synchronous or asynchronous D, T, or JK registers
(clocked-SR registers, which are a subset of JK, are also
possible). See Figure 5. EEPROM memory cells are used
for programming the desired configuration. Four sum-of-
product logic functions (SUM terms A, B, C and D) are fed
into each LCC from the logic array. Each SUM term can be
selectively used for multiple functions as listed below.
3 04-02-052D
Commercial/Industrial
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D
R
P
Q
D R e g is te r
Q = D a fte r clo cke d
B e st fo r sto ra g e , sim p le co u n te rs,
sh ifte rs a n d sta te m a ch in e s w ith
fe w h o ld (lo o p ) co n d itio n s.
T
R
P
Q
T R e g is te r
Q to g g le s w h e n T = 1
Q h o ld s w h e n T = 0
B e st fo r w id e b in a ry co u n te rs (sa ve s
p ro d u ct te rm s) a n d sta te m a ch in e s
w ith m a n y h o ld (lo o p ) co n d ition s.
J K R e g is te r
Q to g g le s w h e n J/K = 1 /1
Q h o ld s w h e n J/K = 0 /0
Q = 1 w h e n J/K = 1 /0
Q = 0 w h e n J/K = 0 /1
C o m b in e s fe a tu re s o f b o th D a n d T
re g iste rs.
J
R
P
Q
K
0 8 -1 6 -0 0 5 A
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 11).
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one output can be combinatorial and the
third, an output enable or an additional buried logic
function. The multi-function PEELTM Array logic cells are
equivalent to two or three macrocells of other PLDs, which
have only one output per cell. They also allow registers to
be truly buried from I/O pins without limiting them to input-
only (see Figure 8 and Figure 9).
I/O C ell (IO C )
Input C ell (INC )
R EG /
L atch
Q
M UX
Input
T o
A rray
Input C ell C lock
F rom G lobal C ell
M UX
F rom
Logic
C ontrol
C ell
A ,B ,C
or
Q
M UX
M UX
1 0
D
I/O P in
M UX
T o
A rray
R EG /
L atch
Q
Input C ell C lock
F rom G lobal C ell
Input
Input
0 8-1 6 -00 6 A
Figure 6. I/O Cell Block Diagram
IO C /IN C R e g is te r
Q = D a fte r risin g e d g e o f clock
h o ld s u n til n e xt risin g e dg e
IO C /IN C L a tc h
Q = L w h e n clo ck is h ig h
h o ld s va lu e w h e n clo ck is lo w
L
Q
D
Q
0 8 -1 6 -0 0 7 A
Figure 7. IOC Register Configurations
4 04-02-052D
Commercial/Industrial
Input Cells (INC)
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell. The register is rising edge clocked. The latch is
transparent when the clock is high and latched on the
clock's failing edge. The register/latch can also be
bypassed for a non registered input.
I/O Cell (IOC)
All PEELTM Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. A feature of the 7536 IOC is the use of
SUM-D as a feed-back to the array when the I/O pin is a
dedicated output. This allows for additional buried registers
and logic paths. (See Figure 8 & Figure 9).
I/O w ith
independe nt
output ena ble
I/O
Q
D
Input w ith optional
register/latch
A
B
C
D
1
2
O E
D
Q
0 8 -1 6 -0 08 A
Figure 8. LCC & IOC With Two Outputs
A
B
C
D
O utput
1
2
3
B uried register or
logic paths
Q
D
D
Q
08 -16-009A
Figure 9. LCC & IOC With Three Outputs
Global Cells
The global cells, shown in Figure 10, are used to direct
global clock signals and/or control terms to the LCCs, IOCs
and INCs. The global cells allow a clock to be selected
from the CLK1 pin, CLK2 pin, or a product term from the
logic array (PCLK). They also provide polarity control for
IOC clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-of-
products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 11). The PA7536 provides two
global cells that divide the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
G lobal C ell: LC C & IO C
M U X
M U X
C L K 1
C L K 2
P CL K
R e g -Typ e
P re se t
R e se t
L C C R e se ts
L C C P re se ts
L C C R e g -T yp e
IO C C lo cks
L C C C lo cks
G lobal C ell: IN C
M U X
C L K 1
C L K 2
P CL K
IN C C lo cks
G ro u p A & B
0 8-1 6 -0 1 0 A
Figure 10. Global Cells
R e g is te r T yp e C h a n g e F e a tu re
G lo b a l C e ll ca n d yn a m ica lly cha n g e u se r-
se le cte d L C C re g iste rs fro m D to T o r fro m D
to JK . T h is sa v e s p ro d u ct te rm s fo r lo a d a b le
co u n te rs o r sta te m a ch in e s. U se a s D re g is te r
to lo a d , u se a s T o r JK to co u nt. T im in g a llo w s
d yn a m ic o p era tio n .
T
R
P
Q
D
R
P
Q
R e g-T yp e fro m G lo b al C e ll
E x a m p le :
P ro d u ct te rm s fo r 1 0 b it lo a d ab le b in a ry co u n ter
D u se s 5 7 p ro d u ct te rm s (4 7 co u n t, 1 0 lo a d )
T u se s 3 0 p ro d u ct te rm s (1 0 co u n t, 2 0 lo a d )
D /T u se s 2 0 p ro d u ct te rm s (1 0 co u n t, 1 0 lo a d )
0 8 -1 6 -01 1 A
Figure 11. Register Type Change Feature
5 04-02-052D
Commercial/Industrial
PEELTM Array Development Support
Development support for PEELTM Arrays is provided by
ICT and manufacturers of popular development tools. ICT
offers the powerful WinPLACE Development Software (free
to qualified PLD designers). The WinPLACE software
includes an architectural editor, logic compiler, waveform
simulator, documentation utility and a programmer
interface. The WinPLACE editor graphically illustrates and
controls the PEELTM Array's architecture, making the
overall design easy to understand, while allowing the
effectiveness of boolean logic equations, state machine
design and truth table entry. The WinPLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. WinPLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
waveform display.(See Figure 12, Figure 13 and Figure 14)
Figure 12 - WinPLACE Architectural Editor for
PA7536
PEELTM Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT's
PEELTM Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEELTM Arrays.
Programming
PEELTM Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC, SOIC and TSSOP. This makes
them an ideal development vehicle for the lab. EE-
reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without
waste. Programming of PEELTM Arrays is supported by
popular third party programmers.
Design Security and Signature Word
The PEELTM Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEELTM Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEELTM Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 13 - WinPLACE LCC and IOC screen
Figure 14 - WinPLACE simulator screen
6 04-02-052D
Commercial/Industrial
Table 1. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
Unit
V
CC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
V
I
, V
O
Voltage Applied to Any Pin
Relative to Ground
1
-0.5
to
V
CC
+ 0.6
V
I
O
Output Current
Per pin (I
OL
, I
OH
) 25
mA
T
ST
Storage Temperature
-65 to + 150
C
T
LT
Lead Temperature
Soldering 10 seconds
+300
C
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Unit
Commercial 4.75
5.25
V
CC
Supply
Voltage
Industrial 4.5
5.5
V
Commercial 0
+70
T
A
Ambient
Temperature
Industrial -40
+85
C
T
R
Clock Rise Time
See Note 2
20
ns
T
F
Clock Fall Time
See Note 2
20
ns
T
RVCC
V
CC
Rise Time
See Note 2
250
ms
Table 3. D.C. Electrical Characteristics
Over the Operating Range
Symbol
Parameter
Conditions
Min
Max
Unit
V
OH
Output HIGH Voltage - TTL
V
CC
= Min, I
OH
= -4.0mA
2.4
V
V
OHC
Output HIGH Voltage -
CMOS
V
CC
= Min, I
OH
= -10A
V
CC
- 0.3
V
V
OL
Output LOW Voltage - TTL
V
CC
= Min, I
OL
= 16mA
0.5
V
V
OLC
Output LOW Voltage -
CMOS
V
CC
= Min, I
OL
= -10A
0.15
V
V
IH
Input HIGH Level
2.0
V
CC
+ 0.3
V
V
IL
Input
LOW
Level
-0.3
0.8
V
I
IL
Input Leakage Current
V
CC
= Max, GND
'
IN
'
CC
10
A
I
OZ
Output Leakage Current
I/O = High-Z, GND
'
O
'
CC
10
A
I
SC
Output Short Circuit
Current
4
V
CC
= 5V, V
O
= 0.5V, TA= 25C -30
-120
mA
-15
60
I
CC
11
V
CC
Current
V
IN
= 0V or V
CC
3,11
f = 25MHz
All outputs disabled
4
I-15
45 (typ.)
19
70
mA
C
IN
7
Input Capacitance
5
6 pF
C
OUT
7
Output
Capacitance
5
T
A
= 25C, V
CC
= 5.0V @ f = 1 MHz
12 pF
7 04-02-052D
Commercial/Industrial
Table 4. A.C Electrical Characteristics Combinatorial
Over the Operating Range
-15/I-15
Unit
Symbol
Parameter
6,12
Min
Max
t
PDI
Propagation delay Internal (t
AL
+ t
LC
)
9
ns
t
PDX
Propagation delay External (t
IA
+ t
AL
+t
LC
+ t
LO
)
15
ns
t
IA
Input or I/O pin to array input
2
ns
t
AL
Array input to LCC
8
ns
t
LC
LCC input to LCC output
10
1
ns
t
LO
LCC output to output pin
4
ns
t
OD
, t
OE
Output Disable, Enable from LCC output
7
4
ns
t
OX
Output Disable, Enable from input pin
7
15
ns
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage.
Figure 15. Combinatorial Timing - Waveforms and Block Diagram
8 04-02-052D
Commercial/Industrial
Table 5. A.C. Electrical Characteristics Sequential
-15/I-15
Unit
Symbol
Parameter
6,1
Min
Max
t
SCI
Internal set-up to system clock
8
- LCC
14
(t
AL
+ t
SK
+ t
LC
- t
CK
)
5
ns
t
SCX
Input
16
(EXT.) set-up to system clock, - LCC (t
IA
+ t
SCI
)
7
ns
t
COI
System-clock to Array Int. - LCC/IOC/INC
14
(t
CK
+t
LC
)
7
ns
t
COX
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
11
ns
t
HX
Input hold time from system clock - LCC
0
ns
t
SK
LCC Input set-up to async. clock
13
- LCC
2
ns
t
AK
Clock at LCC or IOC - LCC output
1
ns
t
HK
LCC input hold time from system clock - LCC
4
ns
t
SI
Input set-up to system clock - IOC/INC
14
(t
SK
- t
CK
)
0
ns
t
HI
Input hold time from system clock - IOC/INC (t
SK
- t
CK
)
4
ns
t
PK
Array input to IOC PCLK clock
6
ns
t
SPI
Input set-up to PCLK clock
17
- IOC/INC (t
SK
-t
PK
-t
IA
)
0
ns
t
HPI
Input hold from PCLK clock
17
- IOC/INC (t
PK
+t
IA
-t
SK
)
6
ns
t
SD
Input set-up to system clock - IOC/INC Sum-D
15
(
tIA
+ t
AL
+ t
LC
+ t
SK
- t
CK
)
7
ns
t
HD
Input hold time from system clock - IOC Sum-D
0
ns
t
SDP
Input set-up to PCLK clock
(
tIA
+ t
AL
+ t
LC
+ t
SK
t
pK
) - IOC Sum-D
7
ns
tHDP
Input hold time from PCLK clock - IOC Sum-D
0
ns
t
CK
System-clock delay to LCC/IOC/INC
6
ns
t
CW
System-clock low or high pulse width
6
ns
f
MAX1
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
83.3
MHz
f
MAX2
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
71.4
MHz
f
MAX3
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
62.5
MHz
f
MAX4
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
55.5
MHz
f
TGL
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
9
83.3
MHz
t
PR
LCC presents/reset to LCC output
1
ns
t
ST
Input to Global Cell present/reset (t
IA
+ t
AL
+ t
PR
)
11
ns
t
AW
Asynch. preset/reset pulse width
8
ns
t
RT
Input to LCC Reg-Type (RT)
7
ns
t
RTV
LCC Reg-Type to LCC output register change
1
ns
t
RTC
Input to Global Cell register-type change (t
RT
+ t
RTV
)
8 ns
t
RW
Asynch. Reg-Type pulse width
10
ns
t
RESET
Power-on reset time for registers in clear state
2
5
s
9 04-02-052D
Commercial/Industrial
Figure 16. Sequential Timing Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
for periods less than 20ns.
2.Test points for Clock and V
CC
in t
R
,t
F
,t
CL
,t
CH
, and t
RESET
are referenced at
10% and 90% levels.
3. I/O pins are 0V or V
CC
.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
7. t
OE
is measured from input transition to V
REF
0.1V (See test loads at
end of Section 6 for V
REF
value). t
OD
is measured from input transition
to V
OH
-0.1V or V
OL
+0.1V.
8. "System-clock" refers to pin 1 or pin 28 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of the Data Book.
13. "Async. Clock" refers to the clock from the Sum term (OR gate).
14. The "LCC" term indicates that the timing parameter is applied to the
LCC register. The "IOC" term indicates that the timing parameter is
applied to the IOC register. The "LCC/IOC" term indicates that the
timing parameter is applied to both the LCC and IOC registers. The
"LCC/IOC/INC" term indicates that the timing parameter is applied to
the LCC,IOC, and INC registers.
15. This refers to the Sum-D gate routed to the IOC register for an
additional buried register.
16. The term "input" without any reference to another term refers to an
(external) input pin.
17. The parameter t
SPI
indicates that the PCLK signal to the IOC register
is always slower than the data from the pin or input by the absolute
value of (t
SK
-t
PK
-t
IA
). This means that no set-up time for the data
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
pin must remain stable for t
HPI
time, i.e. to wait for the PCLK signal to
arrive at the IOC register.
18. Typical (typ) ICC is measured at T
A
= 25
C, freq = 25MHZ, V
CC
=
5V
10 04-02-052D
Commercial/Industrial
Table 6. Ordering Information
Part Number
Speed
Temperature
Package
PA7536P-15 C
PA7536PI-15
9/15ns
I
P28
PA7536J-15 C
PA7536JI-15
9/15ns
I
J28
PA7536S-15
C
PA7536SI-15
9/15ns
I
S28
PA7536T-15
C
PA7536TI-15
9/15ns
I
T28
Figure 17. Part Number
D evice S uffix
P A 7 5 3 6 J -1 5
P a c k a g e
P = P lastic 600m il D IP
S = S O IC
J = P lastic (J) Leaded C hip C arrier (P LC C )
T = T S S O P
S p e e d
-15 = 9ns /15ns tpd/tpdx
T e m p e ra tu re R a n g e
(B lank ) = C om m ercial 0 to 70 C
I = Industrial -40 to +85 C
0 8 -1 6 -0 1 7 A
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2123 Ringwood Avenue
San Jose, CA 95131
TEL (408) 434-0678
FAX (408) 432-0815
Email:
sales&marketing@ictpld.com
Website:
http://www.ictpld.com
2000 Integrated Circuit Technology Corp.
ICT reserves the right to make changes in specifications at any time and without notice. The information furnished by ICT
in this publication is believed to be accurate and reliable. However, no responsibility is assumed by ICT for its use nor for
any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents
or patent rights of ICT. ICT's products are not authorized for use as critical components in life support devices or systems.
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