DESCRIPTION:
The LP-StackTM series is a family of interchangeable memory
modules. The 64 Megabit DRAM is a member of this family
which utilizes the new and innovative space saving TSOP
stacking technology. The module is constructed with TWO 16
Meg x 4 EDO, 3.3 Volt DRAM's available in a 128 Megabit
compatible pin-out.
The 64 Megabit based LP-StackTM modules have been
designed to fit in the same footprint as the 32 Meg x 4 DRAM
TSOP monolithic. This allows the memory board designer
to upgrade the memory in their products without redesigning
the memory board, thus saving time and money.
FEATURES:
Configuration Available:
128 Megabit: 32 Meg x 4
Access Times: 50, 60ns (max.)
3.3 Volt Supply
Common Data Inputs and Outputs
Extended Data Out Capability (EDO)
4K/8K 64ms Refresh
3 Variations of Refresh:
- RAS only Refresh
- CAS before RAS Refresh
- Hidden Refresh
Package: Leadless TSOP Module
A0-A11
Row Address:
A0-A11
Column Address: A0-A11
Refresh Address: A0-A11
A0-A12* Row
Address:
A0-A12
Column Address: A0-A10
Refresh Address: A0-A12
DQ0-DQ3
Data In/Data Out
CAS0-CAS1
Column Address Strobes
RAS0-RAS1
Row Address Enables
WE
Data Write Enables
OE
Data Output Enables
V
DD
Power Supply (+3.3V)
Vss
Ground
N.C.
No Connect
30A221-10
REV. B 8/01
This document contains information on a product that is currently released to production at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
128 Megabit CMOS 3.3V EDO DRAM
DP3ED32MX4RKY5 / DP3ED32MX4R8KY5
1
1
VDD
32 VSS
DQ0 2
31 DQ3
DQ1 3
30 DQ2
N.C. 4
29 N.C.
N.C. 5
28 CAS1
RAS1 6
27 VSS
VDD 7
26 CAS0
WE 8
25 OE
RAS0 9
24 A12
A0 10
23 A11
A1 11
22 A10
A2 12
21 A9
A3 13
20 A8
A4 14
19 A7
A5 15
18 A6
VDD 16
17 VSS
A0-A11
CAS0
RAS0
DQ0-DQ3
WE
OE
*(A0-A12)
16Mx4 DRAM
16Mx4 DRAM
RAS1
CAS1
1
PIN NAMES
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVANCED COMPONENTS PACKAGING
* A12 for 8K refresh device.
C
COMMERCIAL
0C to +70C
60
50
DP
XX
C
-
GRADE
SPEED
3.3 VOLT EDO DRAM
PREFIX
50ns
60ns
3ED
32M
X
4
KY5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
KY5
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
R
64 MEGABIT BASED 4K REFRESH
R
STACKABLE TSOP (RAIL)
64 MEGABIT BASED 8K REFRESH
R8
MANUFACTURER CODE*
XX
-
MEMORY
SUPPLIER
DP
SUPPLIER CODE*
ORDERING INFORMATION
30A221-10
REV . B 8/01
2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
1
1
.502.010
.098 MAX.
.050
.024
.031 [.79]
.841 MAX.
.040
[12.75.25]
[2.49 MAX.]
[21.36 MAX.]
[.79]
[1.27]
[.61]
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2001 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DP3ED32MX4RKY5/DP3ED32MX4R8KY5
128 Megabit CMOS 3.3V EDO DRAM
* Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
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