This document contains information on a product that is currently released to production at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
DESCRIPTION:
The LP-StackTM series is a family of interchangeable memory
modules. The 64 Megabit DRAM is a member of this family
which utilizes the new and innovative space saving TSOP
stacking technology. The module is constructed with two 16
Meg x 4 EDO, 3.3 Volt DRAM's available in a 128 Megabit
compatible pin-out.
The 64 Megabit based LP-StackTM modules have been
designed to fit in the same footprint as the 32 Meg x 4 DRAM
TSOP monolithic. This allows the memory board designer
to upgrade the memory in their products without redesigning
the memory board, thus saving time and money.
FEATURES:
Configuration Available:
128 Megabit: 32 Meg x 4
Access Times: 50, 60ns (max.)
3.3 Volt Supply
Common Data Inputs and Outputs
Extended Data Out Capability (EDO)
4K/8K 64ms Refresh
3 Variations of Refresh:
- RAS only Refresh
- CAS before RAS Refresh
- Hidden Refresh
Package: Leadless TSOP Module
A0-A11
Row Address:
A0-A11
Column Address: A0-A11
Refresh Address: A0-A11
AD-A12* Row
Address:
A0-A12
Column Address: A0-A10
Refresh Address: A0-A12
DQ0-DQ3
Data In/Data Out
CAS0-CAS1
Column Address Strobes
RAS0-RAS1
Row Address Enables
WE
Data Write Enables
OE
Data Output Enables
Vcc
Power Supply (+3.3V)
Vss
Ground
N.C.
No Connect
30A221-00
REV. B 8/01
128 Megabit CMOS 3.3V EDO DRAM
DP3ED32MX4RY5 / DP3ED32MX4R8Y5
PIN 1
23
38
1
Vcc
Vss
36
DQ3
2
DQ1
35
N.C.
3
DQ2
34
N.C.
4
N.C.
33
Vss
5
N.C.
29
A10
6
N.C.
28
A9
7
Vcc
27
A8
8
WE
26
A7
9
A0
25
A6
10
A1
Vss
11
A2
21
19
17
R
AS0
INDEX
20
18
22
R
AS1
Vcc
A4
A5
A3
15
13
14
12
45
46
43
44
42
41
C
AS0
DQ4
37
32
OE
31
30
N.C./(A12)*
A11
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
C
AS1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(TOP VIEW)
16
RAS0
24
39
40
CAS0
47
48
A0-A11
CAS0
RAS0
DQ0-DQ3
WE
OE
*(A0-A12)
16Mx4 DRAM
16Mx4 DRAM
RAS1
CAS1
1
PIN NAMES
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVANCED COMPONENTS PACKAGING
* A12 for 8K refresh device.
C
COMMERCIAL 0C to +70C
60
50
DP
XX
C
-
GRADE
SPEED
3.3 VOLT EDO DRAM
PREFIX
50ns
60ns
3ED
32M
X
4
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
Y5
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
R
64 MEGABIT BASED 4K REFRESH
R
STACKABLE TSOP (RING)
64 MEGABIT BASED 8K REFRESH
R8
MANUFACTURER CODE*
XX
-
MEMORY
SUPPLIER
DP
SUPPLIER CODE*
ORDERING INFORMATION
30A221-00
REV . B 8/01
2
PIN 1
.940.010
.530.010
.024 [.6096]
(.090) [2.286]
(.090) [2.286]
.050
.024
.045
(.095)
.045
.050 [1.27]
INDEX
.045
.045
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
.098 MAX.
[23.876]
[13.462]
[2.4892] MAX.
[1.143]
[1.143]
[2.413]
[.6096]
[1.27]
[1.143]
[1.143]
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2001 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DP3ED32MX4RY5 / DP3ED32MX4R8Y5
128 Megabit CMOS 3.3V EDO DRAM
* Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
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