4 Megabit 3.3 Volt High Speed SRAM
DP3S128X32Y5
ADVANCED INFORMATION
DESCRIPTION:
The DP3S128X32Y5 is the 128K x 32 SRAM module
the utilize the new and innovative space saving TSOP
stacking technology. The module is constructed of four
128K x 8 SRAM's that are configured as 128K x 32.
The DP3S128X32Y5 provides for a compatible upgrade
path to lower density compatible modules. The
module features high speed access times with common
data inputs and outputs.
FEATURES:
Organizations Available:
128K x 32, 256K x 16 or 512K x 8
Access Times: 10, 12, 15ns
Fully Static Operation
- No clock or refresh required
Single +3.3V Power Supply, 10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Package: 64-Pin TSOP Stack
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
PIN NAMES
A0 - A16
Address
I/O0 - I/O31
Data Input / Output
CE0 - CE3
Low Chip Enables
WE
Write Enable
OE
Output Enable
V
DD
Power (+3.3V)
VSS
Ground
N.C.
No Connect
30A236-04
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DP3S128X32Y5
Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DC OPERATING CHARACTERISTICS:
Over Operating Ranges
Symbol
Characteristics
Test Condition
Min.
Max.
Unit
I
IN
Input
Leakage Current
V
IN
= 0V to V
DD
-8
+8
A
I
OUT
Output
Leakage Current
V
I/O
= 0V to V
DD ,
CE or OE = V
IH
or WE = V
IL
-2
+2
A
I
CC
Operating
Supply Current
Cycle = min., Duty = 100%,
I
OUT
= 0mA
X8
355
mA
X16
450
X32
640
I
SB1
Full Standby
Standby Current
V
IN
V
DD
-0.2V or
V
IN
V
SS
+0.2V
180
mA
I
SB2
Standby Current (TTL)
CE = V
IH
260
mA
V
OL
Output LOW Voltage
I
OL
= 8.0mA
0.4
V
V
OH
Output HIGH Voltage
I
OH
= -4.0mA
2.4
V
Note:
Typical measurements made at +25
C. Cycle = min., V
DD
= 5.0V.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max.
Unit
V
DD
Supply Voltage
3.0 3.3
3.6
V
V
IH
Input HIGH Voltage 2.0
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.3
2
0.8
V
T
A
Operating
Temperature
C
0
+25
+70
C
CI -40 +25
+85
CAPACITANCE
4
:
T
A
= +25
C, F = 1.0MHz
Symbol
Parameter
Max. Unit Condition
C
ADR
Address Input
35
pF
V
IN2
= 0V
C
CE
Chip Enable
15
C
WE
Write Enable
35
C
OE
Output Enable
35
C
I/O
Data Input/Output
15
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
5ns*
Input and Output
Timing Reference Levels
1.5V
OUTPUT LOAD
Load
C
L
Parametric Measured
1
30pF
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
2
5pF
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
and t
WHZ
TRUTH TABLE
Mode
CEn WE OE
I/O Pin
Supply
Current
Not Selected
H
X
X
HIGH-Z
Standby
D
OUT
Disable
L
H
H
HIGH-Z
Active
Read
L
H
L
D
OUT
Active
Write
L
L
X
D
IN
Active
H = HIGH L = LOW X = Don't Care
ABSOLUTE MAXIMUM RATING
3
Symbol
Parameter
Max.
Unit
T
STC
Storage Temperature
-65 to +150
C
T
BIAS
Temperature Under Bias
-55 to +125
C
V
DD
Supply Voltage
1
-0.5 to +4.6
V
V
I/O
Input/Output Voltage
1
-0.5 to +4.6
V
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions Min. Max. Unit
V
OH
HIGH Voltage
I
OH
= -4mA
2.4
V
V
OL
LOW Voltage
I
OL
=8mA
0.4
V
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+3.3V
319
353
C
L
*
D
OUT
30A236-04
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Dense-Pac Microsystems, Inc.
DP3S128X32Y5
ADVANCED INFORMATION
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over Operating Ranges
No.
Symbol
Parameter
10ns
12ns
15ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RC
Read Cycle Time
10
12
15
ns
2
t
AA
Address Cycle Time
10
12
15
ns
3
t
CO
Chip Enable Access Time
10
12
15
ns
4
t
OE
Output Enable to Output Valid
5
6
7
ns
5
t
CLZ
Chip Enable to Output in LOW-Z
4, 6
3
3
3
ns
6
t
OLZ
Output Enable to Output in LOW-Z
4, 5
0
0
0
ns
7
t
CHZ
Chip Enable to Output in HIGH-Z
4, 5
0
5
0
6
0
7
ns
8
t
OHZ
Output Enable to Output in HIGH-Z
4, 5
0
5
0
6
0
7
ns
9
t
OH
Output Hold from Address Change
3
3
3
ns
AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE:
Over Operating Ranges
6, 7
No.
Symbol
Parameter
10ns
12ns
15ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
10
t
WC
Write Cycle Time
10
12
15
ns
11
t
AW
Address Valid to End of Write
8
9
10
ns
12
t
CW
Chip Enable to End of Write
8
9
10
ns
13
t
SA
Address Setup Time *
0
0
0
ns
14
t
WP
Write Pulse Width (OE High)
8
9
10
ns
15
t
WP1
Write Pulse Width (OE Low)
10
12
14
ns
16
t
WR
Write Recovery Time
0
0
0
ns
17
t
WHZ
Write Enable to Output in HIGH
4, 5
0
5
0
6
0
7
ns
18
t
DW
Data to Write Time Overlap
6
6
7
ns
19
t
DH
Data Hold Time form Write Time
0
0
0
ns
20
t
OW
Output Active from End of Write
4, 5
3
3
3
ns
* Valid for both Read and Write Cycles.
READ CYCLE 1:
Address Controlled WE is HIGH CE and OE are LOW.
ADDRESS
DATA I/O
30A236-04
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DP3S128X32Y5
Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
READ CYCLE :
CE is Controlled. WE is HIGH.
WRITE CYCLE 1:
OE Clock.
ADDRESS
CE
OE
DATA I/O
ADDRESS
CE
CE
WE
DATA IN
DATA OUT
30A236-04
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Dense-Pac Microsystems, Inc
.
DP3S128X32Y5
ADVANCED INFORMATION
WRITE CYCLE 2:
OE is LOW.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
30A236-04
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