32 Megabit CMOS SRAM
DP3S1MX32PY5
DESCRIPTION:
The DP3S1MX32PY5 is a 1M x 32 SRAM module that utilizes the
new and innovative space saving TSOP stacking technology.
The module is constructed of two 1M x 16 SRAM's that are
configured as a 1M x 32.
The DP3S1MX32PY5 module features high speed access times
with common data inputs and outputs.
FEATURES:
Organizations Available: 1M x 32
Access Times: 10*, 12, 15, 20ns
3.3
0.3** Volt Power Requirement
Fully Static Operation - No clock or refresh required
TTL-Compatible Inputs and Outputs
80-Pin Surface Mount LP-Stack TM
* 0-70 only.
** 5% for 10ns only.
1
30A244-00
REV. B
ADVANCED
INFORMATION
PIN NAMES
A0 - A19
Address Inputs
I/O0 - I/O31
Data Input/Output
CS
Stack Enable
WE
Write Enable
OE
Output Enable
BS0
Byte Select I/O0 - I/O7
BS1
Byte Select I/O8 - I/O15
BS2
Byte Select I/O16 - I/O23
BS3
Byte Select I/O24 - I/O31
V
DD
Power (+3.3V)
V
SS
Ground
NU.
Not Usable
This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc.
Dense-Pac reserves the right to change or discontinue information on this product without prior notice.
FUNCTIONAL BLOCK DIAGRAM
BS0
WE
I/O0-I/O15
1Mx16
S
RAM
BS1
OE
BS2
A0-A19
BS3
CS
1Mx16
S
RAM
I/O16-I/O31
A0-A19
OE
WE
LB
UB
CE
LB
UB
CE
PIN-OUT DIAGRAM
PIN 1
INDEX
28
TOP VIEW
I/O12
1
77
VDD
2
I/O13
3
I/O14
4
VSS
5
I/O15
6
A4
7
A3
8
A2
9
A1 10
A0 11
BS1 12
CS 13
VDD 14
WE 15
BS3 16
A19 17
A18 18
76
29
75
30
74
31
73
32
72
33
71
34
70
35
69
36
68
37
38
39
78
40
80
79
19
A17
21
A15
I/O0 22
A16 20
41
I/O4
42
VDD
43
I/O5
44
I/O6
45
VSS
46
I/O7
47
A14
48
A13
49
A12
50
A11
51
A10
52
BS0
53
NU
54
VSS
55
OE
56
BS2
57
A9
58
A8
VDD
I/O28
I/031
VSS
I/O30
I/O29
VDD
I/O24
VSS
I/O27
VSS
I/O26
I/O25
I/O19
I/O18
VSS
I/O20
VDD
I/O21
I/O22
VSS
I/O23
VSS
I/O16
VDD
I/O17
I/O2
I/O3
VSS
I/O1
VDD
25
27
26
24
23
66
65
64
63
62
67
60
59
61
A6
A7
I/O10
I/O9
VDD
I/O8
A5
VSS
I/O11
DP3S1MX32PY5
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
4
Symbol
Characteristic
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
10ns
3.135
3.3
3.465
V
12, 15, 20ns
3.0
3.3
3.6
V
IH
Input HIGH Voltage
2.0
V
DD
+0.3
3
V
V
IL
Input LOW Voltage
-0.3
2
0.8
V
T
A
Operating Temperature
C
0
+25
+70
o
C
CI
-40
+25
+85
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
Characteristics
Test Conditions
Min.
Max.
Unit
I
IN
Input Leakage Current
V
IN
= 0V to V
DD
, V
DD
= max.
-2
+2
A
I
OUT
Output Leakage Current
V
I/O
= 0V to V
DD
, V
DD
= max., CE = V
IH
-1
+1
A
I
CC
Dynamic Operating Current
CE = V
IL
, V
DD
= max., I
OUT
= 0mA, f = f max.
900
mA
I
SB1
Full Standby Supply Current
(CMOS)
f = 0, V
IN
V
DD
-0.2V or
V
IN
V
SS
+0.2V, CE
V
DD
-0.2V
8
mA
I
SB2
Standby Current (TTL)
CE = V
IH
, f = f max.
210
mA
V
OL
Output Low Voltage
I
OUT
= +2.0mA
0.4
V
V
OH
Output High Voltage
I
OUT
= -2.0mA
2.4
V
ADVANCED
INFORMATION
2
30A244-00
REV. B
CAPACITANCE
5
:
T
A
= 25
C, F = 1.0MHz
Symbol
Parameter
Max.
Unit
Condition
C
ADR
Address Input
20
pF
V
IN
2
= 0V
C
CE
Chip Enable
20
C
BS
Byte Select
15
C
WE
Write Enable
20
C
OE
Output Enable
20
C
I/O
Data Input/Output
15
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions
Min.
Max. Unit
V
OH
HIGH Voltage
I
OH
= -2mA
2.4
V
V
OL
LOW Voltage
I
OL
= +2mA
0.4
V
ABSOLUTE MAXIMUM RATINGS
4
Symbol
Parameter
Value
Unit
T
STC
Storage Temperature
-55 to +125
C
T
BIAS
Temperature Under Bias
-55 to +125
C
V
DD
Supply Voltage
1
-0.5 to +4.6
V
V
I/O
Input/Output Voltage
1
-0.5 to +4.6
V
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
2ns
Input and Output Timing Reference Levels
1.5V
OUTPUT LOAD
Load
C
L
Parameters Measured
1
30pF
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
2
5pF
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+3.3V
780
1200
C
L
*
D
OUT
Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
3
30A244-00
REV. B
ADVANCED
INFORMATION
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
Parameter
10ns
12ns
15ns
20ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RC
Read Cycle Time
10
12
15
20
ns
2
t
AA
Address Access Time
10
12
15
20
ns
3
t
CO
CE to Output Valid
10
12
15
20
ns
4
t
OE
Output Enable to Output Valid
5
6
8
9
ns
5
t
BA
Byte Enable Access Time
5
6
8
9
ns
6
t
LZ
CE to Output in LOW-Z
5, 6
3
3
3
3
ns
7
t
OLZ
Output Enable to Output in LOW-Z
5, 6
1
1
1
1
ns
8
t
BLZ
Byte Enable to Output in LOW-Z
1
1
1
1
ns
9
t
HZ
CE to Output in HIGH-Z
5, 6
6
7
8
9
ns
10
t
OHZ
Output Enable to Output in HIGH-Z
5, 6
6
7
8
9
ns
11
t
BHZ
Byte Enable to Output in HIGH-Z
6
7
8
9
ns
12
t
OH
Output Hold from Address Change
3
3
3
3
ns
TRUTH TABLE
Mode
CS
OE
WE
BS0
BS1
BS2
BS3
I/O0-
I/O7
I/O8-
I/O15
I/O16-
I/O23
I/O24-
I/O31
Supply
Current
Read
L
L
H
L
L
L
L
D
OUT
D
OUT
D
OUT
D
OUT
Active
H
L
L
L
High-Z
D
OUT
D
OUT
D
OUT
L
H
L
L
D
OUT
High-Z
D
OUT
D
OUT
L
L
H
L
D
OUT
D
OUT
High-Z
D
OUT
L
L
L
H
D
OUT
D
OUT
D
OUT
High-Z
Write
L
X
L
L
L
L
L
D
IN
D
IN
D
IN
D
IN
Active
H
L
L
L
High-Z
D
IN
D
IN
D
IN
L
H
L
L
D
IN
High-Z
D
IN
D
IN
L
L
H
L
D
IN
D
IN
High-Z
D
IN
L
L
L
H
D
IN
D
IN
D
IN
High-Z
Output Data
L
H
H
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Active
L
X
X
H
H
H
H
High-Z
High-Z
High-Z
High-Z
Standby
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Standby
H = HIGH
L = LOW
X = Don't Care
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
7, 8
:
Over operating ranges
No. Symbol
Parameter
10ns
12ns
15ns
20ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
13
t
WC
Write Cycle Time
10
12
15
20
ns
14
t
AW
Address Valid to End of Write
8.5
9
11
15
ns
15
t
CW
Chip Enable to End of Write
8.5
9
11
15
ns
16
t
BW
Byte Enable to End of Write
8.5
9
11
15
ns
17
t
AS
Address Set-Up Time *
0
0
0
0
ns
18
t
WP
Write Pulse Width (OE High)
7
8
10
12
ns
19
t
WR
Write Recovery Time, CE, WE
0
0
0
0
ns
20
t
WHZ
Write Enable to Output in HIGH-Z
5, 6
6
7
8
10
ns
21
t
DW
Data to Write Time Overlap
6
7
8
10
ns
22
t
DH
Data Hold from Write Time
0
0
0
0
ns
23
t
OW
Output Active from End of Write
1
1
1
1
ns
* Valid for both Read and Write Cycles.
DP3S1MX32PY5
Dense-Pac Microsystems, Inc.
4
30A244-00
REV. B
ADVANCED
INFORMATION
READ CYCLE
ADDRESS
CE
OE
BS0 - BS3
DATA OUT
WRITE CYCLE 1: WE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED
INFORMATION
5
30A244-00
REV. B
WRITE CYCLE 2: CE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
WRITE CYCLE 3: UB, LB Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
DP3S1MX32PY5
Dense-Pac Microsystems, Inc.
6
30A244-00
REV. B
ADVANCED
INFORMATION
MECHANICAL DRAWING
ORDERING INFORMATION
NOTES:
1.
All voltages are with respect to V
SS
.
2.
-1.5V min. (Pulse Width
4ns) for I
20mA.
3.
V
IH
(max.)=V
DD
+1.5Vdc (Pulse Width
4ns) for I
20mA.
4.
Stresses greater than those under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
5.
This parameter is guaranteed and not 100% tested.
6.
Transition is measured at the point of
500mV from steady state
voltage.
7.
When OE and CE are LOW and WE is HIGH, I/O pins are in the output
state,and input signals of opposite phase to the outputs must not be
applied.
7.
The outputs are in a high impedance state when WE is LOW.
9.
Chip Enable and Write Enable can initiate and terminate WRITE Cycle.
[24.77.25]
.975.010
[12.75.25]
.502.010
.150 MAX.
[3.81 MAX.]
PIN 1
INDEX
(X2)
.0375 [.95]
.020 [.51]
.078 [1.98]
(X4)
.0315 [.80] BSC
.0325 [.83] (X2)
.0315 [.80]
.020 [.51]
BSC
7321 lincoln way, garden grove, california 92841-1431
(714) 898-0007
(800) 642-4477
fax: (714) 897-1772
http://www.dense-pac.com
C
COMMERCIAL
0C to +70C
12
DP
nn
C
-
GRADE
SPEED
3.3 VOLT CMOS SRAM
PREFIX
12ns
3S
1M
X
32
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
P
80-PIN LP-STACK
CI
COMMERCIAL PROCESSED-
20
20ns
-40C to +85C
INDUSTRIAL TEMPERATURE
16 MEG BASED DEVICES
15
15ns
10
10ns
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