4 Megabit High Speed CMOS SRAM
DPS512M8MKH/DPS512M8MKJ
DESCRIPTION:
The DPS512M8MKH/DPS512M8MKJ are 4,194,304
bit High Speed Satic Random Access Memory
monolithics organised as 524,288 words by 8 bits.
The DPS512M8MKH/DPS512M8MKJ uses 8 common
input and output lines and has an output enable pin
which operates faster than address access time at read
cycle. The device is fabricated using advanced CMOS
process and designed for high-speed circiut
technology. It is particularly well suited for use in
high-density high-speed system applications.
This 4-Megabit CMOS static RAM device is packaged
in a 400 mil 36-pin plasic SOJ or TSOP package.
FEATURES:
Organizations Available: 512K x 8
Access Times: 10, 12, 15ns
Low Power Dissipation:
Standby:
(TTL)
40mA (max.)
(CMOS) 10mA (max.)
Operating:
10 : 200mA (max.)
12 : 190mA (max.)
15 : 180mA (max.)
Single +5.0V Power Supply,
10% Tolerance
TTL Compatible Inputs and Outputs
Input/Output Compatable with 3.3V Device
Fully Static Operation
- No clock or refresh required
Three State Output
Center Power/Ground Pin Configuration
Standard Pin Configuration
Packages Available:
DPS512M8MKJ: 36-Pin SOJ
DPS512M8KH:
36-Pin TSOP2w
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A18
Address Inputs
I/O1 - I/O8
Data Input/Output
CE
Low Chip Enable
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
512Kx8, 20 - 45ns, STACK/DIP
30A129-11
D
PIN-OUT DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A197-00
REV. 1
1
DPS512M8MKH/DPS512M8MKJ
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max.
Unit
V
DD
Supply Voltage
4.5
5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
T
A
Operating
Temperature
C
0
+25
+70
o
C
TRUTH TABLE
Mode
CE
WE
OE
I/O Pin Supply
Current
Not Selected
H
X
X
High-Z Standby
D
OUT
Disable
L
H
H
High-Z Active
Read
L
H
L
D
OUT
Active
Write
L
L
X
D
IN
Active
H = HIGH L = LOW X = Don't Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions
Min. Max. Unit
V
OH
HIGH Voltage
I
OH
= -4.0mA 2.4
V
V
OL
LOW Voltage
I
OL
=8.0mA
0.4
V
ABSOLUTE MAXIMUM RATINGS
3
Symbol
Parameter
Value
Unit
T
STC
Storage Temperature
-65 to +150
C
T
BIAS
Temperature Under Bias
-0 to +70
C
V
DD
Supply Voltage
1
-0.5 to +7.0
C
V
I/O
Input/Output Voltage
1
-0.5 to V
DD
+0.5
V
CAPACITANCE
4
: T
A
= 25
C, F = 1.0MHz
Symbol
Parameter
Max.
Unit
Condition
C
ADR
Address Input
7
pF
V
IN
2
= 0V
C
CE
Chip Enable
7
C
WE
Write Enable
7
C
OE
Output Enable
7
C
I/O
Data Input/Output
8
+5V
255
480
C
L
*
D
OUT
Figure 1. Output Load
* Including Probe and Jig Capacitance.
OUTPUT LOAD
Load
C
L
Parameters Measured
1
100pF
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
2
5pF
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
5ns
Input and Output
Timing Reference Levels
1.5V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
Characteristics
Test Conditions
Typ.
()
C
Unit
Min.
Max.
I
IN
Input Leakage Current
V
IN
= 0V to V
DD
-
-5
+5
A
I
OUT
Output Leakage Current
V
I/O
= 0V to V
DD
,
CE = V
IH
, or WE = V
IL
-
-5
+5
A
I
CC
Operating
Supply Current
Cycle=min., Duty=100%
I
OUT
= 0mA
10ns
-
200
mA
12ns
-
190
15ns
-
180
I
SB1
Full Standby
Supply Current
V
IN
V
DD
-0.2V or
V
IN
V
SS
+0.2V
-
10
mA
I
SB2
Standby Current (TTL)
CE = V
IH
-
40
mA
V
OL
Output Low Voltage
I
OUT
= 8.0mA
-
0.4
V
V
OH
Output High Voltage
I
OUT
= -4.0mA
-
2.4
V
Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
30A197-00
REV. 1
2
Dense-Pac Microsystems, Inc.
DPS512M8MKH/DPS512M8MKJ
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
Parameter
10ns
12ns
15ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RC
Read Cycle Time
10
12
15
ns
2
t
AA
Address Access Time
10
12
15
ns
3
t
CO
CE to Output Valid
10
12
15
ns
4
t
OE
Output Enable to Output Valid
5
6
7
ns
5
t
LZ
CE to Output in LOW-Z
4, 5
3
3
3
ns
6
t
OLZ
Output Enable to Output in LOW-Z
4, 5
0
0
0
ns
7
t
HZ
CE to Output in HIGH-Z
4, 5
5
6
7
ns
8
t
OHZ
Output Enable to Output in HIGH-Z
4, 5
0
5
0
6
0
7
ns
9
t
OH
Output Hold from Address Change
3
3
3
ns
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
Parameter
10ns
12ns
15ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
10
t
WC
Write Cycle Time
10
12
15
ns
11
t
AW
Address Valid to End of Write
7
8
10
ns
12
t
CW
Chip Enable to End of Write
7
8
10
ns
13
t
AS
Address Set-Up Time *
0
0
0
ns
14
t
WP
Write Pulse Width
7
8
10
ns
15
t
WR
Write Recovery Time
0
0
0
ns
16
t
WHZ
Write Enable to Output in HIGH-Z
4, 5
0
5
0
6
0
7
ns
17
t
DW
Data to Write Time Overlap
5
6
7
ns
18
t
DH
Data Hold from Write Time
0
0
0
ns
19
t
OW
Output Active from End of Write
3
3
3
ns
* Valid for both Read and Write Cycles.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
30A197-00
REV. 1
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DPS512M8MKH/DPS512M8MKJ
Dense-Pac Microsystems, Inc.
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid
Transition from
Transition from
Data Undefined
HIGH to LOW
LOW to HIGH
or Don't Care
30A197-00
REV. 1
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Dense-Pac Microsystems, Inc.
DPS512M8MKH/DPS512M8MKJ
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1.
All voltages are with respect to V
SS
.
2.
-2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V
at DC level).
3.
Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4.
This parameter is guaranteed and not 100% tested.
5.
Transition is measured at the point of
500mV from steady
state voltage.
6.
When OE and CE are LOW and WE is HIGH, I/O pins are
in the output state,and input signals of opposite phase to
the outputs must not be applied.
7. The outputs are in a high impedance state when WE is
LOW.
8.
CE and WE can initiate and terminate WRITE Cycle.
ORDERING INFORMATION
30A197-00
REV. 1
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DPS512M8MKH/DPS512M8MKJ
Dense-Pac Microsystems, Inc.
MECHANICAL DRAWING
36-Pin SOJ
36-Pin TSOP2
Dense-Pac Microsystems, Inc.
7321 Lincoln Way Garden Grove , California 92841-1431
(714) 898-0007 (800) 642-4477
(Outside CA)
FAX: (714) 897-1772 http://www.dense-pac.com
30A197-00
REV. 1
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