16 Megabit High Speed CMOS SRAM
DPS512X32BV3
DESCRIPTION:
The DPS512X32BV3 `'VERSA-STACK'' module is a
revolutionary new high speed memory subsystem using
Dense-Pac Microsystems' ceramic Stackable Leadless
Chip Carriers (SLCC) mounted on a co-fired ceramic
substrate. It offers 16 Megabits of SRAM in a package
envelope of 1.090 x 1.090 x 0.776 inches.
The DPS512X32BV3 contains sixteen individual
128K x 8 SRAMs, packaged in their own hermetically
sealed SLCCs making the module suitable for
commercial, industrial and military applications.
By using SLCCs, the `'Versa-Stack'' family of modules
offers a higher board density of memory than available
with conventional through-hole, surface mount, module,
or hybrid techniques.
FEATURES:
Organizations Available:
512K x 32, or 1M x 16
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Low Power Dissipation:
32mW (typ.) Full Standby
1.6W (typ.) Operating (x8)
Single +5V Power Supply,
10% Tolerance
TTL Compatible
Common Data Inputs and
Outputs
Low Data Retention Current:
80
A typ. (2.0V)
66-Pin PGA `'VERSA-STACK''
Package
*
Commercial only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O31
Data Input/Output
CE0 - CE7
Chip Enables
WE0, WE1
Write Enables
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A044-12
REV. D
1
DPS512X32BV3
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max.
Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
T
A
Operating
Temperature
M/B -55 +25
+125
o
C
I
-40 +25
+85
C
0
+25
+70
TRUTH TABLE
Mode
CE
WE
OE
I/O Pin Supply
Current
Not Selected
H
X
X
High-Z Standby
D
OUT
Disable
L
H
H
High-Z Active
Read
L
H
L
D
OUT
Active
Write
L
L
X
D
IN
Active
H = HIGH L = LOW X = Don't Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions
Min. Max. Unit
V
OH
HIGH Voltage
I
OH
= -4.0mA 2.4
V
V
OL
LOW Voltage
I
OL
=8.0mA
0.4
V
ABSOLUTE MAXIMUM RATINGS
3
Symbol
Parameter
Value
Unit
T
STC
Storage Temperature
-65 to +150
C
T
BIAS
Temperature Under Bias
-55 to +125
C
V
DD
Supply Voltage
1
-0.5 to +7.0
C
V
I/O
Input/Output Voltage
1
-0.5 to V
DD
+0.5
V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
Characteristics
Test Conditions
Typ.
()
C
I
M/B
Unit
Min.
Max.
Min.
Max.
Min.
Max.
I
IN
Input
Leakage Current
V
IN
= 0V to V
DD
-
-80
+80
-80
+80
-80
+80
A
I
OUT
Output
Leakage Current
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
-
-40
+40
-40
+40
-40
+40
A
I
CC
Operating
Supply Current
Cycle=min.,
Duty=100%, I
OUT
= 0mA
X16
550
700
770
810
mA
X32
700
920
980
1060
I
SB1
Full Standby
Supply Current
V
IN
V
DD
-0.2V or
V
IN
V
SS
+0.2V, CE
V
DD
-0.2V
6.4
80
80
160
mA
I
SB2
Standby Current (TTL)
CE = V
IH
400
480
560
560
mA
I
DR3
Data Retention
Supply Current
(3.0V)
V
DR
= 3.0V, CE
V
DR
-0.2V
1.12
6.4
9.6
32.0
mA
I
DR2
Data Retention
Supply Current
(2.0V)
V
DR
= 2.0V, CE
V
DR
-0.2V
0.56
4.0
6.4
28.8
mA
V
OL
Output Low Voltage
I
OUT
= 8.0mA
-
0.4
0.4
0.4
V
V
OH
Output High Voltage
I
OUT
= -4.0mA
-
2.4
2.4
2.4
V
Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
CAPACITANCE
4
: T
A
= 25
C, F = 1.0MHz
Symbol
Parameter
Max.
Unit
Condition
C
ADR
Address Input
140
pF
V
IN
2
= 0V
C
CE
Chip Enable
40
C
WE
Write Enable
90
C
OE
Output Enable
140
C
I/O
Data Input/Output
60
30A044-12
REV. D
2
Dense-Pac Microsystems, Inc.
DPS512X32BV3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
Parameter
20ns
25ns
30ns
35ns
45ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RC
Read Cycle Time
20
25
30
35
45
ns
2
t
AA
Address Access Time
20
25
30
35
45
ns
3
t
CO
Chip Enable to Output Valid
20
25
30
35
45
ns
4
t
OE
Output Enable to Output Valid
8
10
15
20
25
ns
5
t
LZ
Chip Enable to Output in LOW-Z
4, 5
3
3
3
3
3
ns
6
t
OLZ
Output Enable to Output in LOW-Z
4, 5
0
0
0
0
0
ns
7
t
HZ
Chip Enable to Output in HIGH-Z
4, 5
10
12
15
20
25
ns
8
t
OHZ
Output Enable to Output in HIGH-Z
4, 5
8
10
15
20
25
ns
9
t
OH
Output Hold from Address Change
3
3
3
3
3
ns
Available in Commercial Only.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
Parameter
20ns
25ns
30ns
35ns
45ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
10
t
WC
Write Cycle Time
20
25
30
35
45
ns
11
t
AW
Address Valid to End of Write
15
20
25
30
40
ns
12
t
CW
Chip Enable to End of Write
15
20
25
30
40
ns
13
t
AS
Address Set-Up Time ***
0
0
0
0
0
ns
14
t
WP
Write Pulse Width
15
20
25
30
35
ns
15
t
WR
Write Recovery Time
0
0
0
0
0
ns
16
t
WHZ
Write Enable to Output in HIGH-Z
4, 5
8
10
12
15
20
ns
17
t
DW
Data to Write Time Overlap
12
15
15
20
25
ns
18
t
DH
Data Hold from Write Time
0
0
0
0
0
ns
19
t
OW
Output Active from End of Write
3
3
3
3
3
ns
*** Valid for both Read and Write Cycles.
+5V
255
480
C
L
**
D
OUT
Figure 1.
Output Load
** Including Probe and Jig Capacitance.
OUTPUT LOAD
Load
C
L
Parameters Measured
1
30pF
except t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
2
5pF
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
5ns
Input and Output
Timing Reference Levels
1.5V
* Transision measured between 0.8 and 2.2V.
Data Retention AC Characteristics
8
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
V
DD
for Data
Retention
CE
V
DR
-0.2V,
V
IN
V
DR
-0.2V or V
IN
V
SS
+0.2V
2.0
-
-
V
V
CDR
Chip Disable to
Data Retention Time
See Data Retention Waveform
0
-
-
ns
t
R
Operation Recovery Time
See Data Retention Waveform
5
-
-
ms
30A044-12
REV. D
3
DPS512X32BV3
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
V
DD
-0.2V
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-12
REV. D
4
Dense-Pac Microsystems, Inc.
DPS512X32BV3
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-12
REV. D
5
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