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Электронный компонент: DPS512X32CV3

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16 Megabit High Speed CMOS SRAM
DPS512X32CV3
DESCRIPTION:
The DPS512X32CV3 `'VERSA-STACK'' module is a revolutionary
new high speed memory subsystem using Dense-Pac
Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC)
mounted on a co-fired ceramic substrate. It offers 16 Megabits of
SRAM in a package envelope of 1.090 x 1.090 x 0.776 inches.
The DPS512X32CV3 contains sixteen individual 128K x 8 SRAMs,
packaged in their own hermetically sealed SLCCs making the
module suitable for commercial, industrial and military
applications.
By using SLCCs, the `'Versa-Stack'' family of modules offers a higher
board density of memory than available with conventional
through-hole, surface mount, module, or hybrid techniques.
FEATURES:
Organizations Available:
512K x 32, 1M x 16, 2M x 8
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Low Power Dissipation:
32mW (typ.) Full Standby
1.6W (typ.) Operating (x8)
Single +5V Power Supply,
10% Tolerance
TTL Compatible
Common Data Inputs and
Outputs
Low Data Retention Current:
560
A typ. (2.0V)
66-Pin PGA `'VERSA-STACK''
Package
*
Commercial only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O31
Data Input/Output
CE0 - CE7
Low Chip Enables
SEL0, SEL1
High Chip Enables
WE0, WE1
Write Enables
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A044-13
REV. C
1
DPS512X32CV3
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
3
Symbol
Characteristic
Min. Typ.
Max.
Unit
V
DD
Supply Voltage
4.5
5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
T
A
Operating
Temperature
M/B -55 +25
+125
o
C
I
-40 +25
+85
C
0
+25
+70
TRUTH TABLE
Mode
SEL
CE
WE
OE I/O Pin Supply
Current
Not Selected
L
X
X
X
High-Z Standby
Not Selected
X
H
X
X
High-Z Standby
D
OUT
Disable
H
L
H
H
High-Z Active
Read
H
L
H
L
D
OUT
Active
Write
H
L
L
X
D
IN
Active
H = HIGH L = LOW X = Don't Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
Conditions
Min. Max. Unit
V
OH
HIGH Voltage
I
OH
= -4.0mA 2.4
V
V
OL
LOW Voltage
I
OL
=8.0mA
0.4
V
ABSOLUTE MAXIMUM RATINGS
3
Symbol
Parameter
Value
Unit
T
STC
Storage Temperature
-65 to +150
C
T
BIAS
Temperature Under Bias
-55 to +125
C
V
DD
Supply Voltage
1
-0.5 to +7.0
C
V
I/O
Input/Output Voltage
1
-0.5 to V
DD
+0.5
V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
Characteristics
Test Conditions
Typ.
()
C
I
M/B
Unit
Min.
Max.
Min.
Max.
Min.
Max.
I
IN
Input
Leakage Current
V
IN
= 0V to V
DD
-
-80
+80
-80
+80
-80
+80
A
I
OUT
Output
Leakage Current
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
-
-40
+40
-40
+40
-40
+40
A
I
CC
Operating
Supply Current
Cycle=min., Duty=100%
I
OUT
= 0mA
X8
475
590
665
685
mA
X16
550
700
770
810
X32
700
920
980
1060
I
SB1
Full Standby
Supply Current
V
IN
V
DD
-0.2V or
V
IN
V
SS
+0.2V
6.4
80
80
160
mA
I
SB2
Standby Current (TTL)
CE = V
IH
400
480
560
560
mA
I
DR3
Data Retention
Supply Current
(3V)
V
DR
= 3V, CE
V
DR
-0.2V,
or SEL
0.2V, V
IN
V
DD
-0.2V
or V
IN
+0.2V
1.12
6.4
9.6
32.0
mA
I
DR2
Data Retention
Supply Current
(2V)
V
DR
= 2V, CE
V
DR
-0.2V,
or SEL
0.2V, V
IN
V
DD
-0.2V
or V
IN
+0.2V
0.56
4.0
6.4
28.8
mA
V
OL
Output Low Voltage
I
OUT
= 8.0mA
-
0.4
0.4
0.4
V
V
OH
Output High Voltage
I
OUT
= -4.0mA
-
2.4
2.4
2.4
V
Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
CAPACITANCE
4
: T
A
= 25
C, F = 1.0MHz
Symbol
Parameter
Max.
Unit
Condition
C
ADR
Address Input
140
pF
V
IN
2
= 0V
C
CE
Chip Enable
40
C
SEL
Active High
Chip Select
90
C
WE
Write Enable
90
C
OE
Output Enable
140
C
I/O
Data Input/Output
60
30A044-13
REV. C
2
Dense-Pac Microsystems, Inc.
DPS512X32CV3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
Parameter
20ns*
25ns
30ns
35ns
45ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RC
Read Cycle Time
20
25
30
35
45
ns
2
t
AA
Address Access Time
20
25
30
35
45
ns
3
t
CO1
CE to Output Valid
20
25
30
35
45
ns
4
t
CO2
SEL to Output Valid
20
25
30
35
45
ns
5
t
OE
Output Enable to Output Valid
8
10
15
20
25
ns
6
t
LZ1
CE to Output in LOW-Z
4, 5
3
3
3
3
3
ns
7
t
LZ2
SEL to Output in LOW-Z
4, 5
3
3
3
3
3
ns
8
t
OLZ
Output Enable to Output in LOW-Z
4, 5
0
0
0
0
0
ns
9
t
HZ1
CE to Output in HIGH-Z
4, 5
10
12
15
20
25
ns
10
t
HZ2
SEL to Output in HIGH-Z
4, 5
10
12
15
20
25
ns
11
t
OHZ
Output Enable to Output in HIGH-Z
4, 5
8
10
15
20
25
ns
12
t
OH
Output Hold from Address Change
3
3
3
3
3
ns
* Available in Commercial Only.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
Parameter
20ns*
25ns
30ns
35ns
45ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
13
t
WC
Write Cycle Time
20
25
30
35
45
ns
14
t
AW
Address Valid to End of Write
15
20
25
30
40
ns
15
t
CW
Chip Enable to End of Write
15
20
25
30
40
ns
16
t
AS
Address Set-Up Time **
0
0
0
0
0
ns
17
t
WP
Write Pulse Width
15
20
25
30
35
ns
18
t
WR
Write Recovery Time
0
0
0
0
0
ns
19
t
WHZ
Write Enable to Output in HIGH-Z
4, 5
8
10
12
15
20
ns
20
t
DW
Data to Write Time Overlap
12
15
15
20
25
ns
21
t
DH
Data Hold from Write Time
0
0
0
0
0
ns
22
t
OW
Output Active from End of Write
3
3
3
3
3
ns
* Available in Commercial Only.
** Valid for both Read and Write Cycles.
+5V
255
480
C
L
*
D
OUT
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
OUTPUT LOAD
Load
C
L
Parameters Measured
1
30pF
except t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
,
and t
WHZ
2
5pF
t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
, and
t
WHZ
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
5ns
Input and Output
Timing Reference Levels
1.5V
30A044-13
REV. C
3
DPS512X32CV3
Dense-Pac Microsystems, Inc.
DATA RETENTION WAVEFORM:
SEL Controlled.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
SEL
V
DR2
0.4V
0V
SEL
-0.2V
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
V
DD
-0.2V
Data Retention AC Characteristics
8
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DR
V
DD
for Data
Retention
CE
V
DR
-0.2V, SEL
V
DR
-0.2V,
or V
IN
V
DR
-0.2V or V
IN
0.2V
2.0
-
-
V
V
CDR
Chip Disable to
Data Retention Time
See Data Retention Waveform
0
-
-
ns
t
R
Operation Recovery Time
See Data Retention Waveform
5
-
-
ms
30A044-13
REV. C
4
Dense-Pac Microsystems, Inc.
DPS512X32CV3
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-13
REV. C
5
DPS512X32CV3
Dense-Pac Microsystems, Inc.
WRITE CYCLE 2:
WE Controlled. OE is HIGH.
8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3:
WE Controlled. OE is LOW.
8, 9
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-13
REV. C
6
Dense-Pac Microsystems, Inc.
DPS512X32CV3
ORDERING INFORMATION
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way u Garden Grove, California 92841-1428
(714) 898-0007 u (800) 642-4477
(Outside CA)
u FAX: (714) 897-1772 u http://www.dense-pac.com
NOTES:
1. All voltages are with respect to V
SS
.
2. -2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V at DC
level).
3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of
500mV from steady state
voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the
output state,and input signals of opposite phase to the outputs must
not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. SEL timing is the same as CE timing. The Waveform is inverted.
9. Chip Enable and Write Enable can initiate and terminate WRITE
Cycle.
30A044-13
REV. C
7
30A044-13
REV. C
8