PIN NAMES
A0-A12
Row Address:
A0-A12
Column Address:
A0-A9, A11
BA0, BA1
Bank Select Address
DQ0-DQ3
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
DQM
Data Input/Output Mask
CKE
Clock Enables
CLK
System Clock
CS0 - CS1
Chip Selects
V
DD/
V
SS
Power Supply/Ground
V
DDQ/
V
SSQ
Data Output Power/Ground
NC
No Connect
DESCRIPTION:
The Memory StackTM series is a family of interchangeable memory devices. The 512 Megabit SDRAM Narrow Rail assembly
utilizes the space saving LP-StackTM technology to increase memory density. This stack is constructed with two 256Mb
(64M x 4) SDRAMs.
This 512Mb LP-StackTM has been designed to fit in the
same footprint as the 256Mb (64M x 4) SDRAM TSOPII
monolithic. This stack allows for system upgrade while
providing an alternative low cost memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers' datasheets
Memory organization:
(2) 256Mb memory devices. Each device arranged
as 64M x 4 bits (16M x 4 bits x 4 banks)
Memory stack organization:
128M x 4 bits (32M x 4 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and
footprint (with 2 CSs and 1 CKE)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII Narrow Rail stack
30A215-01
REV. E 2/03
This document contains information on a product under consideration for development at DPAC Technologies Corp.
DPAC reserves the right to change or discontinue information on this product without prior notice.
512 Megabit Narrow Rail SDRAM
DPSD128MX4WNY5
1
ADVAN C E D C O M P O N E NTS PAC K AG I N G
FUNCTIONAL BLOCK DIAGRAM
A0-A12
CAS
WE
CS1
256 Mb SDRAM
DQ0-DQ3
CS0
(16M x 4bit x 4 bank)
RAS
CKE
CLK
DQM
BA0,BA1
(16M x 4 bit x 4 bank)
PINOUT DIAGRAM
(TOP VIEW)
33
A8
VDD
1
N.C.
2
54
VSS
VDDQ
3
53
N.C.
N.C.
4
52
VSSQ
DQ0
5
51
N.C.
VSSQ
6
50
DQ3
N.C.
7
49
VDDQ
N.C.
8
48
N.C.
VDDQ
9
47
N.C.
N.C.
10
46
VSSQ
DQ1
11
45
N.C.
VSSQ
12
44
DQ2
N.C.
13
43
VDDQ
VDD
14
42
N.C.
CS1
15
41
VSS
WE
16
40
N.C.
CAS
17
39
DQM
RAS
18
38
CLK
CS0
19
37
CKE
BA0
20
36
A12
BA1
21
35
A11
A10
22
34
A9
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VDD
27
28
VSS
1
30A215-01
REV. D 1/03
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, LP-StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPSD128MX4WNY5
512 Megabit Narrow Rail SDRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers' specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215C.
ORDERING INFORMATION
DP
-
PREFIX
SD 128M
X
4
NY5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
W
STACKABLE TSOP WITH NARROW RAILS
SYNCHRONOUS DRAM
SUPPLIER
- DP
SUPPLIER CODE *
256 MEGABIT LVTTL BASED
MFR ID
XX
REVISION
MEMORY
X
BLANK
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
n
70P2
75P2
75
55
60
70
TIME
XXX
CYCLE
10
08
12
P12
P13
7.5ns (133MHz) CL3
5.5ns (183MHz) CL3
7ns (143MHz) CL3
6ns (166MHz) CL2
7ns (133MHz) CL2
7.5ns (133MHz) CL2
PC100 / CL2
12ns (83MHz)
8ns (125MHz)
10ns (100MHz)
PC100 / CL3
MECHANICAL DIAGRAM
.020 [.51] TYP
.0315 [.80] TYP
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
PIN 1
INDEX
.478
.102 MAX. [.259 MAX]
.891 MAX.
12.19
[22.63 MAX.]
-.002
+.006
-.05
+.15
[ ]
Lead Toe-to-Toe per device datasheet
Inch [mm]
END VIEW DETAIL
.463 [11.76] TYP
COPLANARITY:
.004 [.10] from seating plane
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