DESCRIPTION:
The LP-StackTM series is a family of interchangeable memory
modules. The 128 Megabit SDRAM is a member of this family
which utilizes the new and innovative space saving TSOP
stacking technology. The modules are constructed with
4 Meg x 16 SDRAMs.
This 128 Megabit LP-StackTM module, DPSD4MX32RY5, has
been designed to allow 32 Output Data lines utilizing two 4
Meg x16 SDRAM TSOP monolithics. Utilizing this LP-StackTM
family allows the memory board designer to upgrade the
memory in their products without redesigning the memory
board, thus saving time and money.
FEATURES:
Configuration Available:
4 Meg x 32 bit
Clock Frequency:
66, 83, 100, 125, 133 MHz (max.)
PC100 and PC133 Compatible
3.3V Supply
LVTTL Compatible I/O
Four Bank Operation
Programmable Burst Type, Burst Length, and CAS Latency
4096 Cycles / 64 ms
Auto and Self Refresh
Package: TSOP Leadless Stack
A0-A11
Row Address:
A0-A11
Column Address: A0-A7
BA0,BA1
Bank Select Address
DQ0-DQ31
Data In/Data Out
CS
Chip Select
CAS
Column Address Strobe
RAS
Row Address Enable
WE
Data Write Enable
UDQM0,UDQM1 Upper Data Input/Output Masks
LDQM0,LDQM1 Lower Data Input/Output Masks
CKE
Clock Enable
CLK
System Clock
V
DD
/Vss
Power Supply/Ground
Vcc
Q
/Vss
Q
Data Output Power/Ground
30A225-02
REV. E 8/01
This document contains information on a product presently under development at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
128 Megabit Synchronous DRAM
DPSD4MX32RY5
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16
BA0
17
VSS
CS
15
18
DQ20
RAS
14
19
DQ21
CAS
13
20
DQ22
WE
12
21
DQ23
LDQM0
11
22
VDD
VDD
10
23
DQ19
DQ7
9
24
DQ18
VSSQ
8
25
DQ17
DQ6
7
26
DQ16
DQ5
6
27
VDD
VDDQ
5
28
N.C.
DQ4
4
29
VSS
DQ3
3
30
A7
VSSQ
2
31
A5
DQ2
1
32
A6
A0
A10/AP
BA1
VDD
DQ0
VDDQ
DQ1
44
43
42
41
40
39
38
37
36
35
34
33
45
46
47
48
A11
A8
A9
A4
A1
LDQM1
VDD
A3
A2
CKE
N.C.
CK
51
50
49
DQ24
DQ25
DQ26
DQ27
75
VSS
76
UDQM1
77
78
79
80
59
60
61
DQ12
VSSQ
DQ11
UDQM0
DQ9
VDDQ
DQ10
58
57
56
55
52
53
54
VSS
N.C.
DQ8
68
69
VSS
N.C.
VSSQ
VSS
DQ15
67
66
65
62
63
64
DQ14
DQ13
VDDQ
DQ31
VDD
74
73
70
71
72
DQ29
DQ30
DQ28
(TOP VIEW)
DM
CAS
WE
DQ16-DQ31
CS
4Mx16 SDRAM
RAS
LDQM0
CK
A0-A11
CKE
4Mx16 SDRAM
BA0-BA1
DQ0-DQ15
LDQM1
UDQM1
UDQM0
1
PIN NAMES
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVANCED COMPONENTS PACKAGING
MANUFACTURER CODE
P1
DP
XX
XX
-
SPEED
MEMORY
PREFIX
PC100
SD
4M
X
32
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
R
STACKABLE TSOP
SYNCHRONOUS DRAM
10ns (100MHz)
8ns (125MHz)
08
10
SUPPLIER
- DP
SUPPLIER CODE
64 MEGABIT LVTTL BASED
15
12
12ns (83MHz)
15ns (66MHz)
CL
X
GRADE
X
CAS LATENCY 2
2
Commercial Temperature
Blank
[1]
[1]
[1]
75
7.5ns (133MHz)
ORDERING INFORMATION
30A225-02
REV. E 8/01
2
Dimensions - Inches [mm]
.015
[0.38]
.062
[1.57] (X4)
.502.008
[12.75.20]
.975.010
[24.77.25]
.155 MAX.
[3.94] MAX.
.0275
[0.79]
.042
[0.79]
.0315
[0.80]
.078
[2.01] (X4)
.020
[0.51]
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2001 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS StackTM are trademarks of DPAC Technologies Corp.
DPSD4MX32RY5
128 Megabit Synchronous DRAM
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NOTE: [1] Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
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