A0-A11
Row Address:
A0-A11
Column Address: A0-A7
BA0,BA1
Bank Select Address
DQ0-DQ31
Data In/Data Out
CS
Chip Select
CAS
Column Address Strobe
RAS
Row Address Enable
WE
Data Write Enable
UDQM0,UDQM1 Upper Data Input/Output Masks
LDQM0,LDQM1 Lower Data Input/Output Masks
CKE
Clock Enable
CLK
System Clock
V
DD
/Vss
Power Supply/Ground
V
DDQ
/Vss
Q
Data Output Power/Ground
N.C.
No connect
DESCRIPTION:
The Memory StackTM series is a family of interchangeable
memory modules. The 256 Megabit SDRAM is a member of
this family which utilizes the space saving LP-StackTM TSOP
stacking technology. The modules are constructed with two 8
Meg x 16 SDRAMs.
This 256 Megabit LP-StackTM module, DPSD8MX32TY5, has
been designed to allow 32 Output Data lines utilizing two
8 Meg x 16 SDRAM TSOP monolithics. This allows system
upgrade without electrical or mechanical redesign, providing
an immediate and low cost memory solution.
FEATURES:
Configuration:
8 Meg x 32 bit (2 Banks x 2M x 16 Bit x 4 Banks)
JEDEC Approved Footprint and Pinout
IPC-A-610 Manufacturing Standards
Assemble per DPAC Application Note 53A001-00
Package: 80-Pin LP-StackTM
The Following Features are not affected by LP StackTM and
are provided as reference only. Refer to memory OEM Device
specification for details:
Clock Frequency is determined by OEM memory device
used.
3.3 Volt DQ Supply
LVTTL Compatible I/O
Four Bank Operation
Programmable Burst Type, Burst Length, and CAS
Latency
Refresh: 4096 Cycles / 64ms
Refresh Types: Auto and Self
30A225-12
REV. F 10/02
This document contains information on a product presently under development at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
256 Megabit Synchronous DRAM
DPSD8MX32TY5
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16
BA0
17
VSS
CS
15
18
DQ20
RAS
14
19
DQ21
CAS
13
20
DQ22
WE
12
21
DQ23
LDQM0
11
22
VDD
VDD
10
23
DQ19
DQ7
9
24
DQ18
VSSQ
8
25
DQ17
DQ6
7
26
DQ16
DQ5
6
27
VDD
VDDQ
5
28
N.C.
DQ4
4
29
VSS
DQ3
3
30
A7
VSSQ
2
31
A5
DQ2
1
32
A6
A0
A10/AP
BA1
VDD
DQ0
VDDQ
DQ1
44
43
42
41
40
39
38
37
36
35
34
33
45
46
47
48
A11
A8
A9
A4
A1
LDQM1
VDD
A3
A2
CKE
N.C.
CK
51
50
49
DQ24
DQ25
DQ26
DQ27
75
VSS
76
UDQM1
77
78
79
80
59
60
61
DQ12
VSSQ
DQ11
UDQM0
DQ9
VDDQ
DQ10
58
57
56
55
52
53
54
VSS
N.C.
DQ8
68
69
VSS
N.C.
VDDQ
VSS
DQ15
67
66
65
62
63
64
DQ14
DQ13
VSSQ
DQ31
VDD
74
73
70
71
72
DQ29
DQ30
DQ28
(TOP VIEW)
DM
CAS
WE
DQ16-DQ31
CS
(2 Meg x 16 Bit x 4 Banks)
RAS
LDQM0
CK
A0-A11
CKE
BA0-BA1
DQ0-DQ15
LDQM1
UDQM1
UDQM0
128Mb SDRAM
(2 Meg x 16 Bit x 4 Banks)
1
PIN NAMES
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
ADVAN C E D C O M P O N E NTS PAC K AG I N G
MANUFACTURER CODE *
P1
DP
XX
XX
-
SPEED
MEMORY
PREFIX
PC100
SD
8M
X
32
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MEMORY MODULE WITHOUT SUPPORT LOGIC
DEPTH
WIDTH
DESIG
T
STACKABLE TSOP
SYNCHRONOUS DRAM
10ns (100MHz)
8ns (125MHz)
08
10
SUPPLIER
- DP
SUPPLIER CODE *
128 MEGABIT LVTTL BASED
15
12
12ns (83MHz)
15ns (66MHz)
CL
X
GRADE
X
CAS LATENCY 3
3
Commercial Temperature
Blank
75
7.5ns (133MHz)
CAS LATENCY 2
2
60
6ns (166MHz)
5.5ns (183MHz)
55
70
7ns (143MHz)
PART NUMBER DESCRIPTION
30A225-12
REV. F 10/02
2
Dimensions - Inches [mm]
.502.008
[12.75.20]
.975.010
[24.77.25]
.155 MAX.
[3.94] MAX.
.0275 [0.79]
.042 [0.79]
.020
[0.51]
Recomended pad layout.
.378
[9.60] BSC
.819 [20.8] BSC
.422
[10.72]
.0315 [0.80]
.020 [0.51] X54
TOP VIEW
END VIEW
SIDE VIEW
BOTTOM VIEW
.522
[13.26]
.0315 [0.80]
PAD PITCH
52X
.0315 [0.80] 24X
.062 [1.57]
.016 [0.41]
.004
.937 [23.80]
.018 [0.46] X26
.0315 [0.80]
Stencil recomendation: .020 round on .018 pads. One to one on .020 x .050 pads.
Stencil .006 thick.
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2002 DPAC Technologies, all rights reserved. DPAC TechnologiesTM, Memory StackTM, System StackTM, CS-StackTM are trademarks of DPAC Technologies Corp.
DPSD8MX32TY5
256 Megabit Synchronous DRAM
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* Contact your sales representative for supplier and manufacturer codes.
MECHANICAL DRAWING
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