Document No. E0418E30 (Ver. 3.0)
Date Published June 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004
DATA SHEET
512MB DDR2 SDRAM SO-DIMM
EBE52UD6ABSA
(64M words
64 bits, 2 Ranks)
Description
The EBE52UD6ABSA is 64M words
64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 8 pieces of 512M bits DDR2
SDRAM sealed in FBGA (
BGA
) package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 4 bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write
are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each FBGA (
BGA) on
the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free
1.8V power supply
Data rate: 533Mbps/400Mbps (max.)
1.8V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(Component)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8
s average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation.
EBE52UD6ABSA
Data Sheet E0418E30 (Ver. 3.0)
4
Pin Description
Pin name
Function
A0 to A12
Address input
Row address
A0 to A12
Column address
A0 to A9
A10 (AP)
Auto precharge
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE Write
enable
/CS0, /CS1
Chip select
CKE0, CKE1
Clock enable
CK0, CK1
Clock input
/CK0, /CK1
Differential clock input
DQS0 to DQS7, /DQS0 to /DQS7
Input and output data strobe
DM0 to DM7
Input mask
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0, SA1
Serial address input
VDD Power
for
internal
circuit
VDDSPD
Power for serial EEPROM
VREF Input
reference
voltage
VSS Ground
ODT0, ODT1
ODT control
NC No
connection
EBE52UD6ABSA
Data Sheet E0418E30 (Ver. 3.0)
5
Serial PD Matrix
Byte
No. Function
described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex
value Comments
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
128
bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256
bytes
2
Memory
type
0 0 0 0 1 0 0 0 08H
DDR2
SDRAM
3
Number
of
row
address
0 0 0 0 1 1 0 1 0DH
13
4
Number
of
column
address
0 0 0 0 1 0 1 0 0AH
10
5
Number
of
DIMM
ranks
0 1 1 0 0 0 0 1 61H
2
6
Module
data
width
0 1 0 0 0 0 0 0 40H
64
7
Module
data
width
continuation
0 0 0 0 0 0 0 0 00H
0
8
Voltage
interface
level
of
this
assembly 0 0 0 0 0 1 0 1 05H
SSTL
1.8V
9
DDR SDRAM cycle time, CL = 5
-5C
0 0 1 1 1 1 0 1 3DH
3.75ns*
1
-4A
0 1 0 1 0 0 0 0 50H
5.0ns*
1
10
SDRAM access from clock (tAC)
-5C
0 1 0 1 0 0 0 0 50H
0.5ns*
1
-4A
0 1 1 0 0 0 0 0 60H
0.6ns*
1
11
DIMM
configuration
type
0 0 0 0 0 0 0 0 00H
None.
12
Refresh
rate/type
1 0 0 0 0 0 1 0 82H
7.8
s
13
Primary
SDRAM
width
0 0 0 1 0 0 0 0 10H
16
14
Error
checking
SDRAM
width
0 0 0 0 0 0 0 0 00H
None.
15
Reserved
0 0 0 0 0 0 0 0 00H
0
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0 0 0 0 0 1 0 0 04H
4
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
3,
4,
5
19
Reserved
0 0 0 0 0 0 0 0 00H
0
20
DIMM
type
information
0 0 0 0 0 1 0 0 04H
SO-DIMM
21
SDRAM
module
attributes
0 0 0 0 0 0 0 0 00H
Normal
22
SDRAM
device
attributes:
General 0 0 1 1 0 0 0 0 30H
VDD
0.1V
23
Minimum clock cycle time at CL = 4
-5C
0 0 1 1 1 1 0 1 3DH
3.75ns*
1
-4A
0 1 0 1 0 0 0 0 50H
5.0ns*
1
24
Maximum data access time (tAC) from
clock at CL = 4
-5C
0 1 0 1 0 0 0 0 50H
0.5ns*
1
-4A
0 1 1 0 0 0 0 0 60H
0.6ns*
1
25
Minimum
clock
cycle
time
at
CL
=
3 0 1 0 1 0 0 0 0 50H
5.0ns*
1
26
Maximum data access time (tAC) from
clock at CL = 3
0 1 1 0 0 0 0 0 60H
0.6ns*
1
27
Minimum
row
precharge
time
(tRP) 0 0 1 1 1 1 0 0 3CH
15ns
28
Minimum row active to row active
delay (tRRD)
0 0 1 0 1 0 0 0 28H
10ns
29
Minimum
/RAS
to
/CAS
delay
(tRCD)
0 0 1 1 1 1 0 0 3CH
15ns
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
45ns
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